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hot - swap controller and digital power monitor with pmbus interface adm1275 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result f rom its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one te chnology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 C 2011 analog devices, inc. all rights reserved. features controls supply voltages from 2 v to 20 v 3 7 0 ns response time to s hort c ircuit resistor - programmable 5 mv to 25 mv c urrent limit 1 % accurate, 12 - bit adc for current, v in /v out readback charge - pumped gate drive for multiple external n - channel fets high gate drive voltage to ensure lowest r dson foldback for tighter fet soa protection automatic retry or latch - off on current fault programmable current limit timer for soa programmable , multifunction gpos power - g ood s tatus output analog uv and ov protec tion enable pin ( adm1275 - 3 only) peak d etect r egisters for current and voltage pmbus fast m ode compliant interface 16- lead qsop and 20 - lead qsop and lfcsp applications power monitoring and control/power b udgeting central office e quipment telecommunication and d ata communication e quipment pc s/s ervers applications diagram q 1 gate sense+ timer timer adm1275-1 gnd r sense sense? vcc v cp 2v to 20v 2.95v to 20v vcap iout uv ov 1.0v 1.0v vout vout 12-bit adc scl sda adr sense+ iout ldo charge pump timeout gpo2/alert2 pwrgd gpo1/alert1/conv latch timer on timer on v cbos ss current limit flb iset timeout current limit control ref select 1.0v gate drive/ logic logic and pmbus 50 + + ? ? + ? + ? 08931-001 figure 1. general description the adm1275 is a hot - swap controller that allows a circuit board to be removed from or inserted into a live backplane. it also features current and voltage readback via an integrated 12 - bit analog - to - digital converter (adc), accessed using a pmbus ? interface. the load current is measured using an internal current sense amplifier that meas ures the voltage across a sense resistor in the power path via the sense+ and sense ? pin s . a default limit of 20 mv is set , but this limit can be adjusted , if required , using a resistor divider network from the internal ref erence voltage to the iset pin. the adm1275 limits the current through the sense resistor by controlling the gate voltage of an external n - channel fet in the power path, via t he gate pin. the sense voltage and, therefore, the load current is maintained below the preset maximum. the adm12 75 protects the external fet by limiting the time that the fet remains on while the current is at its maximum value. this current limit time is set by the choice of capacitor connected to the timer pin. in addition, a foldback resistor network can be used to actively lower the current limit as the voltage across the fet is increased. this helps to maintain constant power in the fet and allows the safe operating area (soa) to be adhered to in an effective manner. in case of a short - circuit event, a fast inte rnal overcurrent detec - tor respond s within 37 0 ns and signal s the gate to shut down. a 1 500 ma pull - down device ensure s a fast fet response. the adm1275 features overvoltage and undervoltage protection, programmed using external resistor dividers on the uv and ov pins. a pwrgd signal can be used to detect when the output supply is valid, using the flb pin to monitor the output. gpo pins can be configured as various output signals that can be assert ed when a programmed current or voltage level is reached. th e 12- bit adc can measure the current in the sense resistor, as well as the supply voltage on the sense+ pin or the output voltage. a pmb us interface allows a controller to read current and voltage data from the adc. measurements can be initiated by a pmbus command. alternatively, the adc can run continu - ously, and the user can read the latest conversion data whenever required. up to four unique pmb us addresses can be selected, depending on the way th at the adr pin is connected. the adm1275 - 1 and adm1275 - 3 a re available in a 20 - lead qsop and 20 - lead lfcsp and have a latch pin that can be configured for automatic retry or latch - off when an overcurrent fault occurs. the adm1275 - 2 is available in a 16 - lead qsop with latch - off mode only .
adm1275 rev. b | page 2 of 48 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 applications diagram ...................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 serial bus timing characteristics .............................................. 7 absolute maximum ratings ............................................................ 8 thermal charac teristics .............................................................. 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 14 functional block diagrams ........................................................... 20 theory of operation ...................................................................... 21 powering the adm1275 ............................................................ 21 current sense inputs .................................................................. 21 current limit reference ............................................................ 22 setting the current limit (iset) .............................................. 22 soft start ...................................................................................... 23 foldback ....................................................................................... 23 timer ............................................................................................ 24 hot - swap retry duty cycle ...................................................... 24 fet gate drive clamps ............................................................. 24 fast response to severe overcurrent ...................................... 25 undervoltage and overvoltage ................................................. 25 enable input (adm1275 - 3 only) ........................................ 25 power good ................................................................................. 25 vout measurement ................................................................. 26 fet health .................................................................................. 26 power monitor ............................................................................ 26 pmbus interface ............................................................................. 27 device addressing ...................................................................... 27 smbus protocol usage ............................................................... 27 packet error checking ............................................................... 27 smbus message form ats ........................................................... 28 group commands ...................................................................... 29 hot - swap control commands ................................................. 30 adm1275 in formation commands ........................................ 30 status commands ....................................................................... 30 gpo and alert pin setup commands ..................................... 31 power monitor commands ...................................................... 31 warning limit setup commands ............................................ 32 pmbus direct format conversion .......................................... 32 voltage and current conversion using lsb values ............... 33 adm1275 alert pin behavior ...................................................... 34 faults and warnings .................................................................. 34 generating an alert ................................................................... 34 handling/clearing an alert ...................................................... 34 smbus alert response address ............................................... 35 example use of smbus alert response address ................... 35 pmbus command reference ........................................................ 36 operation .............................................................................. 37 clear_faults ........................................................................ 37 capability .............................................................................. 37 vout_ov_warn_limit ..................................................... 37 vout_uv_warn_limit ..................................................... 37 iout_oc_warn_limit ...................................................... 37 iout_warn2_limit ............................................................. 38 vin_ov_warn_limit ......................................................... 38 vin_uv_warn_limit ......................................................... 38 status_byte .......................................................................... 38 status_word ........................................................................ 38 status_vout ......................................................................... 39 status_iout .......................................................................... 39 status_input ........................................................................ 39 status_mfr_specific ........................................................ 40 re ad_vin ................................................................................. 40 read_vout ............................................................................. 41 read_iout .............................................................................. 41 pmbus_revision .................................................................. 41 mfr_id ....................................................................................... 41 mfr_model ............................................................................ 41 mfr_revision ........................................................................ 42 peak_iout ............................................................................... 42 peak_vin .................................................................................. 42 peak_vout ............................................................................. 42 pmon_control ................................................................... 42 pmon_config ....................................................................... 43 alert1_config ..................................................................... 43 alert2_config ..................................................................... 44
adm1275 rev. b | page 3 of 48 device_config ..................................................................... 45 power_cycle ......................................................................... 45 outline dimensions ........................................................................ 46 ordering guide ........................................................................... 47 revision history 6 /1 1 rev . a to rev. b changes to t buf parameter ................................................................ 7 added conditions statemen t to table 2 ....................................... 7 changes to vout pin description , table 5 ............................... 10 changes to vout pin description , table 6 ............................... 13 changes to figure 42 ..................................................................... 19 changes to current sense inputs section .................................... 21 added pmbus direct format conversion section ..................... 32 added voltage and current conversion using lsb values section .................................................................................. 33 changes to handling/clea ring and alert section ...................... 34 10 /10 rev . 0 to rev. a added 20 - lead lfcsp ...................................................... universal changes to table 4 ............................................................................ 8 added figure 4; renumbered figures sequentially ..................... 9 changes to table 5 ............................................................................ 9 added t able 6; renumbered tables sequentially ....................... 11 added figure 7 and table 7 ........................................................... 12 updat ed outline dimensions ........................................................ 4 8 changes to ordering guide ........................................................... 48 9/10 revision 0: initial version
adm1275 rev. b | page 4 of 48 specifications v cc = 2.95 v to 20 v, v cc v sense+ , v sense+ = 2 v to 20 v, v sense = (v sense+ ? v sense? ) = 0 v, t a = ?40c to +85c, unless otherwise noted. table 1 . parameter min typ max unit test conditions /comments power supply operating voltage range, v cc 2.95 20 v under voltage lockout 2.4 2.7 v v cc rising under voltage hysteresis 90 120 mv quiescent c urrent, i cc 5 ma gate on and p ower m onitor r unning uv pin input current, i uv 100 na uv 3.6 v uv threshold, uv th 0.97 1.0 1.03 v uv f alling uv threshold hysteresis, uv hyst 40 50 60 mv uv glitch filter, uv gf 2 7 s 50 mv o verdrive uv propagation d elay, uv pd 5 8 s uv l ow to gate pull - down active ov pin adm1275 - 1 and adm1275 -3 input current, i ov 100 na ov 3.6 v ov threshold, ov th 0 .97 1.0 1.03 v ov r ising ov threshold hysteresis, ov hyst 50 60 70 mv ov glitch filter, ov gf 0.5 1.5 s 50 mv overdrive ov propagation delay , ov pd 1.0 2 s ov h i gh to gate pull - down active sense+ and sense? pins input current, i sensex 150 a per individual pin; sense+, sense? = 20 v input i mbalance, i sense 5 a i sense = ( i sense+ ) ? ( i sense? ) vcap pin internally regulated voltage, v vcap 2.66 2.7 2.74 v 0 a i vcap 100 a; c vcap = 1 f iset pin r eference s elect t hreshold, v isetrsth 1.35 1.5 1.65 v if v iset > v isetrsth , an internal 1 v reference (v clref ) is used i nternal reference , v clref 1 v accuracies included in total sense voltage accuracies gain of c urrent s ense a mplifier, av csamp 50 v/v accuracies included in tota l sense voltage accuracies input current , i iset 100 na v iset v vcap gate pin maximum voltage on t he gate is always clamped to 31 v gate drive voltage, v gate v gate = v gate ? v sense+ 10 12 14 v 1 7 v v cc 8 v ; i gate 5 a 4.5 13 v 20 v v cc 17 v; i gate 5 a 8 10 v v sense+ = v cc = 5 v ; i ga te 5 a 4.5 6 v v sense+ = v cc = 2.9 5 v ; i gate 1 a gate pull - up current, i gateup ?2 0 ?3 0 a v gate = 0 v gate pull -d own current, i gatedn_reg 45 60 75 a v gate 2 v; v iset = 1.0 v; (sense+) ? (sense ? ) = 30 mv gate pull - down current, i gatedn_slow 5 10 15 ma v gate 2 v gate pull - down current, i gatedn_fast 750 1500 2000 ma v gate 1 2 v ; v cc 1 2 v gate holdoff resistance 20 ? v cc = 0 v hot - swap sense voltage hot -s wap sense voltage current limit, v sensecl 19.6 20 20.4 mv v iset > 1.6 5 v ; v f lb > 1.1 2 v ; v gate = ( sense+ ) + 3 v ; i gate = 0 a ; v ss 2 v foldback inactive v gate = (sense+) + 3 v; i gate = 0 a; v ss 2 v 24.6 25 25.4 mv v iset = 1.2 5 v ; v flb > 1.39 5 v 19.6 20 20.4 mv v iset = 1. 0 v ; v flb > 1.12 v 9.6 10 10.4 mv v iset = 0. 5 v ; v flb > 0.5 7 v 4.6 5 5.4 mv v iset = 0.2 5 v ; v flb > 0.29 5 v foldback a ctive 3.5 4 4.5 mv v flb = 0 v ; v gate = (sense+) + 3 v ; i gate = 0 a; v ss 1 v 9.6 10 10.4 mv v iset > 1. 0 v ; v flb = 0. 5 v ; v g ate = (sense+) + 3 v ; i gate = 0 a; v ss 1 v
adm1275 rev. b | page 5 of 48 parameter min typ max unit test conditions /comments circui t breaker offset, v cbos 0.6 0.88 1.12 mv circuit breaker trip voltage, v cb = v sensecl ? v cb os severe overcurrent voltage threshold, v senseoc 40 50 mv v iset = 1. 0 v ; v flb > 1. 1 v ; v ss 2 v 9.5 13.0 mv v iset = 0.25 v; v flb > 1.1 v; v ss 2 v sho rt glitch filter duration 90 200 ns v iset > 1.6 5 v; v sense driven from 18 mv to 52 mv; selectable via pmbus long glitch filter duration (default) 530 900 ns v sense driven from 18 mv to 52 mv response time with short glitch filter 1 8 0 370 ns 2 mv overdrive maximum severe overcurrent threshold with long glitch filter 645 1020 ns soft start (ss pin) ss pull - up current, i ss ?12 ?10 ?8 a v ss = 0 v default v sensecl limit 0.5 1.25 1.8 mv when v sense reaches this level, i ss is enabled , ramping v sensecl ; v ss = 0 v ss pull - down current 100 a v ss = 1 v timer pin timer pull - up current (por), i timeruppor ?2 ?3 ?4 a initi al power - on reset; v timer = 0.5 v timer pull - up current (oc fault), i ti meru pflt ? 57 ?60 ? 63 a overcurrent fault; 0.2 v v timer 1 v timer pull - down current (retry), i timerdnrt 1.7 2 2.3 a after fault when gate is off; v timer = 0.5 v timer retry/oc f ault current ratio 3.33 3.8 % defines the limits of the autoretry duty cycle timer pull - down current (hold), i timerdnhold 100 a holds timer at 0 v when inactive; v timer = 0.5 v timer high threshold, v timerh 0.98 1.0 1.02 v timer low threshold, v tim erl 0.18 0.2 0.22 v foldback (flb pin) flb and pwrgd threshold, v flbth 1.08 1.1 1.12 v flb rising; v iset = 1.0 v input current, i flb 100 na v flb 1. 0 v; v iset = 1.25 v 100 na v vcap v flb 20 v hysteresis current 1.7 2.3 a internal hysteresis voltage 1.9 3.1 mv voltage drop across the internal 1.3 k? resistor power - good glitch filter, pwrgd gf 0.3 0.7 1 s 50 mv overdrive minimum fold back clamp 200 mv accuracies included in total sense voltage accuracies vout pin adm1275 - 1 and adm1275 -3 input current 20 a vout = 20 v latch pin adm1275 - 1 and adm1275 -3 output low voltage, v ol_latch 0.4 v i latch = 1 ma 1.5 v i latch = 5 ma leakage current 100 na v latch 2 v; latch output high -z 1 a v latch = 20 v; latch output high -z gpo1/ alert1 /conv pin (adm1275 - 1 and adm1275 - 2), enable pin (adm1275 -3) no internal pull - up present on these pins output low voltage, v ol_gpo 1 0.4 v i gpo 1 = 1 ma 1.5 v i gpo 1 = 5 ma leakage current 100 na v gpo 1 2 v; gpo output high -z 1 a v gpo 1 = 20 v; gpo output high -z input high voltage, v ih 1.1 v inpu t low voltage, v il 0.8 v gpo2/ alert2 pin adm1275 - 1 and adm1275 -3 output low voltage, v ol_gpo 2 0.4 v i gpo 2 = 1 ma 1.5 v i gpo 2 = 5 ma leakage current 100 na v gpo 2 2 v; gpo output high -z 1 a v gpo 2 = 20 v; gpo output high -z
adm1275 rev. b | page 6 of 48 parameter min typ max unit test conditions /comments pwrgd pin output low voltage, v ol_pwrgd 0.4 v i pwrgd = 1 ma 1.5 v i pwrgd = 5 ma vcc that guarantees valid output 1 v i sink = 100 a ; v ol_pwrgd = 0.4 v leakage current 100 na v pwrgd 2 v; pwrgd output high -z 1 a v pwrgd = 20 v ; pwrgd output high -z current and voltage monitoring current sense absolute error 2 5 mv input r ange ; 128 sample averaging (unless otherwise noted) 0.2 0.7 % v sense = 20 mv; v sense+ = 12 v ; t a = 0c to 65c 0.08 % v sense = 20 mv; v sense + = 12 v ; t a = 25c 1.0 % v sense = 20 mv 0.08 % v sense = 2 0 mv; t a = 25c 0.2 % v sense = 20 mv ; t a = 0c to 65c 1.0 % v sense = 20 mv; 16 sample averaging 0.08 % v sense = 20 mv; 16 sample averaging ; t a = 25c 0.2 % v sense = 20 mv; 1 6 sample averaging ; t a = 0c to 65c 2.8 % v sense = 20 mv; 1 sample averaging 0.09 % v sense = 20 mv; 1 sample averaging ; t a = 25c 0.2 % v sense = 20 mv; 1 sample averaging ; t a = 0c to 65c 0.7 % v sense = 2 5 mv; v sense+ = 12 v 0.04 % v sense = 2 5 mv; v sense+ = 12 v ; t a = 25c 0.15 % v sense = 2 5 mv; v sense+ = 12 v ; t a = 0c to 65c 0.75 % v sense = 2 0 mv; v sense+ = 12 v 0.8 % v sense = 1 5 mv; v sense+ = 12 v 1.1 % v sense = 1 0 mv; v sense+ = 12 v 2.0 % v sense = 5 mv; v sense+ = 12 v 4.3 % v sense = 2.5 mv; v sense+ = 12 v sense+/vout absolute error 1.0 % low input range; input voltage 3 v 1.0 % high input range ; input voltage 10 v adc conversion time 250 305 s 1 sample of voltage and current; from command received to valid data in register 4000 4880 s 16 samples of voltage and current averaged; from command received to valid data in register adr pin address set to 00 0 0.8 v connect to gnd input current for address 00 ?40 ?22 a v adr = 0 v to 0.8 v address set to 01 135 150 165 k? resistor to gnd address set to 10 ?1 +1 a no connect state; maximum leakage current allowed address set to 11 2 v connect to vcap input current for address 11 3 10 a v adr = 2.0 v to vcap; must not exceed the maximum allowable current draw from vcap serial bus digital inputs (sda, scl ) input high voltage, v ih 1.1 v input low voltage, v il 0.8 v output low voltage, v ol 0.4 v i ol = 4 ma input leakage, i leak - pin ?10 +10 a ?5 + 5 a device is not powered nominal bus voltage, v dd 2.7 5.5 v 3 v to 5 v 10% capacitance for sda, scl pin, c pin 5 pf input glitch filter, t sp 0 50 ns
adm1275 rev. b | page 7 of 48 serial bus timing characteristi cs t r = (v il(max) C 0.15) to (v ih3v3 + 0.15) and t f = 0.9v dd t o (v il(max) C 0.15); where v ih3v3 = 2.1 v and v dd = 3.3 v. table 2 . parameter description min typ max unit test conditions/comments f sclk clock frequency 400 khz t buf bus free time 1.3 s following the stop condition of a re ad transaction 4.7 s following the stop condition of a write transaction t hd;sta start hold time 0.6 s t su;sta start setup time 0.6 s t su;sto stop setup time 0.6 s t hd; dat sda hold time 300 900 ns t su;dat sda setup time 100 ns t low scl low time 1.3 s t high scl high time 0.6 s t r scl, sda rise time 20 300 ns t f scl, sda fall time 20 300 ns timing diagram t low t buf t hd;dat t su;dat t su;sta t hd;sta t high t r t f t su;sto p s s p v ih v il v ih v il scl sda 08931-002 figure 2. serial bus timing diagram
adm1275 rev. b | page 8 of 48 absolute maximum ratings table 3. parameter rating vcc pin ?0.3 v to +25 v uv pin ?0.3 v to +4 v ov pin ?0.3 v to +4 v ss pin ?0.3 v to vcap + 0.3 v timer pin ?0.3 v to vcap + 0.3 v vcap pin ?0.3 v to +4 v iset pin ?0.3 v to vcap + 0.3 v latch pin ?0.3 v to +25 v scl pin ?0.3 v to +6.5 v sda pin ?0.3 v to +6.5 v adr pin ?0.3 v to vcap + 0.3 v gpo1/alert1 /conv pin, enable pin ?0.3 v to +25 v gpo2/alert2 pin ?0.3 v to +25 v pwrgd pin ?0.3 v to +25 v flb pin ?0.3 v to +25 v vout pin ?0.3 v to +25 v gate pin (internal supply only) 1 ?0.3 v to +36 v sense+ pin ?0.3 v to +25 v sense? pin ?0.3 v to +25 v v sense (v sense+ ? v sense? ) 0.3 v continuous current into any pin 10 ma storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature, soldering (10 sec) 300c junction temperature 150c 1 the gate pin has internal clamping circuits to prevent the gate pin voltage from exceeding the maximum ratings of a mosfet with v gsmax = 20 v and internal process limits. applying a vo ltage source to this pin externally may cause irreversible damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja unit 16-lead qsop (rq-16) 150 c/w 20-lead qsop (rq-20) 126 c/w 20-lead lfcsp (cp-20-9) 30.4 c/w esd caution
adm1275 rev. b | page 9 of 48 pin configuration s and function descrip tions 1 2 3 4 5 6 7 8 9 1 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 uv ov vcap timer ss iset vcc sense? gate gnd pwrgd flb vout gpo1/alert1/conv adr latch gpo2/alert2 sda scl sense+ adm1275-1 top view (not to scale) 08931-006 figure 3. adm1275 - 1 pin configuration , qsop 1 ov 2 vcap 3 iset 4 ss 5 timer notes 1. solder the exposed paddle to the board to improve thermal dissipation. the exposed paddle can be connected to ground. latch adr gpo1/alert1/conv gpo2/alert2 sda 13 14 15 12 1 1 flb vout gnd pwrgd scl sense+ vcc uv sense? gate 6 7 8 0 1 9 8 1 9 1 0 2 7 1 6 1 08931-109 adm1275-1 top view (not to scale) pin 1 indic a t or figure 4 . adm1275- 1 pin configuration , lfcsp table 5 . adm1275 - 1 pin function descriptions pin no. qsop lfcsp mnemonic description 1 19 vcc positive supply input pin. an undervoltage lockout (uvlo) circuit resets the device when a low supply voltage is detected. gate is h eld low when the supply is below uvlo. during normal operation, this pin should remain greater than or equal to sense+ to ensure that specifications are adhered to. no sequencing is required. 2 2 0 uv u nderv oltage input pin. an external resistor divider i s used from the supply to this pin to allow an internal comparator to detect whether the supply is under the uv limit. 3 1 ov overv oltage input pin. an external resistor divider is used from the supply to this pin to allow an internal comparator to detect whether the supply is above the ov limit. 4 2 vcap i nternal r egulated s upply . a capacitor with a value of 1 f or greater should be placed on this pin to maintain good accuracy. this pin can be used as a reference to program the iset pin voltage. 5 3 i set this pin allows the current limit threshold to be programmed. the default limit is set when this pin is connected directly to vcap. t o ac hieve a user - defined sense voltage, the current limit can be adjusted usi ng a resistor divider from vcap. an exter nal reference can also be used. 6 4 ss soft start pin. a capacitor is used on this pin to set the soft start ramp profile. the voltage on the ss pin controls the current sense voltage limit, which controls the inrush current profile. 7 5 timer timer pin . an external capacitor, c timer , sets an initial timing cycle delay and a fault delay. the gate pin is pulled low when the voltage on the timer pin exceeds the upper threshold. 8 6 latch signals th at th e device is latching off after an o vercurrent fault. the device can be configured for auto matic retry after latch - off by connecting this pin directly back to the uv pin. 9 7 adr pmbus address pin. this pin can be tied to gnd , tied to vcap, left floating, or tied low through a resistor to s et four different pmbus addresses (see the device addressing section) . 10 8 gpo1/ alert1 / conv g e neral - p urpose d igital o utput (gpo1). alert ( alert1 ). this pin can be configured to generate an al ert signal when one or more fault or warning conditions are detected. conversion (conv). this pin can be used as an input signal to control when a power monitor adc sampling cycle begins . at power - up, t his pin defaults to a high i mpedance state. there is no internal pull - up on this pin. 11 9 gpo2/ alert2 g e neral - p urpose d igital o utput (gpo2). alert ( alert2 ). this pin can be configured to generate an alert signal when one or more fault or warning conditions are detected. at power - up, this pin indicates the fet health mode by default. there is no internal pull - up on this pin.
adm1275 rev. b | page 10 of 48 pin no. qsop lfcsp mnemonic description 12 10 sda serial data input/output pin. open - drain input/output. requires an external resistive pull - up. 13 11 scl serial clock pin. open - drain in put . r equires an external resistive pull - up. 14 12 pwrgd p ower - good s ignal . u sed to indicate that the supply is within tolerance. this signal is based on the voltage present on the flb pin . 15 13 flb foldback pin. a foldback resistor divider is placed f rom the source of the fet to this pin. foldback is used to reduce the current limit when the source voltage drops. the foldback feature ensures that the power through the fet is not increased beyond the soa limits. 16 14 vout this pin is used to read back the output voltage usi ng the internal adc. a 1 k? resistor should be inserted in series between the source of a fet and the vout pin. 17 15 gnd chip ground pin. 18 16 gate gate output pin. this pin is the high - side gate drive of an external n - channel fet. this pin is driven by the fet drive contro ller, which uses a charge pump to provide a pull - up current to charge the fet gate pin. the fet drive controller regulates to a maximum load current by regulating the gate pin. gate is held low when the supply is below uvlo. 19 17 sense? negative current sense input pin. a sense resistor between the sense+ pin and the sense? pin sets the analog current limit. the hot - swap operation of the adm1275 controls the external fet gate to maintain the sense voltage (v sense+ ? v sense? ). this pin also connects to the fet drain pin. 20 18 sense+ positive current sense input pin. this pin connects to the main supply input. a sense resistor between the sense+ pin and the sense? pin sets the analog current limit. the hot - swap operation of the adm1275 controls the extern a l fet gate to maintain the sense voltage (v sense+ ? v sense? ). this pin is also used to measure the supply input voltage using the adc. n/a ep epad exposed paddle on underside of lfcsp. solder the exposed paddle to the board to improve thermal dissipation. the exposed paddle can be connected to ground.
adm1275 rev. b | page 11 of 48 1 2 3 4 5 6 7 8 1 6 1 5 1 4 1 3 1 2 11 1 0 9 uv vcap iset adr timer ss vcc sense? gate gnd scl gpo1/alert1/conv sda pwrgd flb sense+ adm1275-2 top view (not to scale) 08931-007 figure 5 . adm1275- 2 pin configuration table 6 . adm1275 - 2 pin function descriptions pin no. mnemonic description 1 vcc positive supply in put pin. an undervoltage lockout (uvlo) circuit resets the device when a low supply voltage is detected. gate is held low when the supply is below uvlo. during normal operation, this pin should remain greater than or equal to sense+ to ensure that specific ations are adhered to. no sequencing is required. 2 uv u nderv oltage input pin. an external resistor divider is used from the supply to this pin to allow an internal comparator to detect whether the supply is under the uv limit. 3 vcap internal regulated supply. a capacitor with a value of 1 f or greater should be placed on this pin to maintain good accuracy. this pin can be used as a reference to program the iset pin voltage. 4 iset this pin allows the current limit threshold to be programmed. the defau lt limit is set when this pin is connected directly to vcap. t o ac hieve a user - defined sense voltage, the current limit can be adjusted usi ng a resistor divider from vcap. an external reference can also be used. 5 ss soft start pin. a capacitor is used on this pin to set the soft start ramp profile. the voltage on the ss pin controls the current sense voltage limit, which controls the inrush current profile. 6 timer timer pin. an external capacitor, c timer , sets an initial timing cycle delay and a fault d elay. the gate pin is pulled low when the voltage on the timer pin exceeds the upper threshold. 7 adr pmbus address pin. this pin can be tied to gnd , tied to vcap, left floating, or tied low through a resistor to set four different pmbus addresses (see th e device addressing section) . 8 gpo1/ alert1 / conv g e neral - p urpose d igital o utput (gpo1). alert ( alert1 ). this pin can be configured to generate an alert signal when one or more fault or warning conditions are detected. conversion (conv). this pin can be used as an input signal to control when a power monitor adc sampling cycle begins . at power - up, t his pin defaults to a high i mpedance state. there is no internal pull - up on this pin. 9 sda seri al data input/output pin. open - drain input/output. requires an external resistive pull - up. 10 scl serial clock pin. open - drain input . r equires an external resistive pull - up. 11 pwrgd p ower - good s ignal . u sed to indicate that the supply is within toleranc e. this signal is based on the voltage present on the flb pin . 12 flb foldback pin. a foldback resistor divider is placed from the source of the fet to this pin. foldback is used to reduce the current limit when the source voltage drops. the foldback feat ure ensures that the power through the fet is not increased beyond the soa limits. 13 gnd chip ground pin. 14 gate gate output pin. this pin is the high - side gate drive of an external n - channel fet. this pin is driven by the fet drive controller, which u ses a charge pump to provide a pull - up current to charge the fet gate pin. the fet drive controller regulates to a maximum load current by regulating the gate pin. gate is held low when the supply is below uvlo. 15 sense? negative current sense input pin. a sense resistor between the sense+ pin and the sense? pin sets the analog current limit. the hot - swap operation of the adm1275 controls the external fet gate to maintain the sense voltage (v sense+ ? v sense? ). this pin also connects to the fet drain pin. 16 sense+ positive current sense input pin. this pin connects to the main supply input. a sense resistor between the sense+ pin and the sense? pin sets the analog current limit. the hot - swap operation of the adm1275 controls the extern al fet gate to maint ain the sense voltage (v sense+ ? v sense? ). this pin is also used to measure the supply input voltage using the adc.
adm1275 rev. b | page 12 of 48 1 2 3 4 5 6 7 8 9 1 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 11 uv ov vcap timer ss iset vcc sense? gate gnd pwrgd flb vout enable adr latch gpo2/alert2 sda scl sense+ adm1275-3 top view (not to scale) 08931-008 figure 6 . adm1275- 3 pin configuration , qsop 1 ov 2 vcap 3 iset 4 ss 5 timer latch adr enable gpo2/alert2 sda 13 14 15 12 1 1 flb vout gnd pwrgd scl sense+ vcc uv sense? gate 6 7 8 0 1 9 8 1 9 1 0 2 7 1 6 1 08931-110 adm1275-3 top view (not to scale) pin 1 indic a t or notes 1. solder the exposed paddle to the board to improve thermal dissipation. the exposed paddle can be connected to ground. figure 7 . adm1275- 3 pin configurati on , lfcsp table 7 . adm1275 - 3 pin function descriptions pin no. qsop lfcsp mnemonic description 1 1 9 vcc positive supply input pin. an undervoltage lockout (uvlo) circuit resets the device when a low supply voltage is detected . gate is held low when the supply is below uvlo. during normal operation, this pin should remain greater than or equal to sense+ to ensure that specifications are adhered to. no sequencing is required. 2 2 0 uv u nderv oltage input pin. an external resistor divider is used from the supply to this pin to allow an internal comparator to detect whether the supply is under the uv limit. 3 1 ov overv oltage input pin. an external resistor divider is used from the supply to this pin to allow an internal comparator to detect whether the supply is above the ov limit. 4 2 vcap i nternal r egulated s upply . a capacitor with a value of 1 f or greater should be placed on this pin to maintain good accuracy. this pin can be used as a reference to program the iset pin volta ge. 5 3 iset this pin allows the current limit threshold to be programmed. the default limit is set when this pin is connected directly to vcap. t o ac hieve a user - defined sense voltage, the current limit can be adjusted usi ng a resistor divider from vcap . an external reference can also be used. 6 4 ss soft start pin. a capacitor is used on this pin to set the soft start ramp profile. the voltage on the ss pin controls the current sense voltage limit, which controls the inrush current profile. 7 5 timer timer pin. an external capacitor, c timer , sets an initial timing cycle delay and a fault delay. the gate pin is pulled low when the voltage on the timer pin exceeds the upper threshold. 8 6 latch signals th at th e device is latching off after an overcurrent fault. the device can be configured for auto matic retry after latch - off by connecting this pin directly back to the uv pin. 9 7 adr pmbus address pin. this pin can be tied to gnd , tied to vcap, left floating, or tied low through a res istor to set four different pmbus addresses (see the device addressing section) . 10 8 enable digital logic input. this input must be high to allow the adm1275 - 3 hot - swap controller to begin a power - up sequence. if this pin is hel d low, the adm1275 - 3 is prevented from powering up. there is no internal pull - up on this pin. 11 9 gpo2/ alert2 g e neral - p urpose d igital o utput (gpo2). alert ( alert2 ). this pin can be configured to generate an alert signa l when one or more fault or warning conditions are detected. at power - up, this pin indicates the fet health mode by default. there is no internal pull - up on this pin. 12 1 0 sda serial data input/output pin. open - drain input/output. requires an external r esistive pull - up. 1 3 11 scl serial clock pin. open - drain input . r equires an external resistive pull - up. 1 4 12 pwrgd p ower - good s ignal . u sed to indicate that the supply is within tolerance. this signal is based on the voltage present on the flb pin . 1 5 13 flb foldback pin. a foldback resistor divider is placed from the source of the fet to this pin. foldback is used to reduce the current limit when the source voltage drops. the foldback feature ensures that the power through the fet is not increased beyo nd the soa limits.
adm1275 rev. b | page 13 of 48 pin no. qsop lfcsp mnemonic description 16 14 vout this pin is used to read back the output voltage using the internal a dc. a 1 k? resistor should be inserted in series between the source of a fet and the vout pin. 1 7 15 gnd chip ground pin. 1 8 16 gate gate output pin. this pin is the high - side gate drive of an external n - channel fet. this pin is driven by the fet drive contro ller, which uses a charge pump to provide a pull - up current to charge the fet gate pin. the fet drive controller regulates to a maximum load current by regulating the gate pin. gate is held low when the supply is below uvlo. 1 9 17 sense? negative current sense input pin. a sense resistor between the sense+ pin and the sense? pin sets the analog current limit. the hot - swap operation of the adm1275 controls the external fet gate to maintain the sense voltage (v sense+ ? v sense? ). this pin also connects to the fet drain pin. 20 18 sense+ positive current sense input pin. this pin connects to the main supply input. a sense resistor between the sense+ pin and the sense? pin sets the analog current limit. the hot - swap operation of the adm1275 controls the extern a l fet gate to maintain the sense voltage (v sense+ ? v sense? ). this pin is also used to measure the supply input voltage using the adc. n/a ep epad exposed paddle on underside of lfcsp. solder the exposed paddle to the board to improve thermal dissipation. the exposed paddle can be connected to ground.
adm1275 rev. b | page 14 of 48 typical performance characteristics 0 1 2 3 4 5 i cc (ma) v cc (v) 2 4 6 8 10 12 14 16 18 20 08931-009 +25 c +85 c ?40 c figure 8. supply current ( i cc ) vs. supply voltage (v cc ) 0 1 2 3 4 5 ?40 ?20 0 i cc (ma) temper a ture ( c) v cc = 20v v cc = 12v v cc = 2.95v 08931-010 20 40 60 80 figure 9. supply current ( i cc ) vs. temperature 0 2 4 6 8 10 12 14 2 4 6 8 12 10 14 16 18 20 i gatedn_slow (ma) v cc (v) 08931-0 1 1 +25 c ?40 c +85 c fig ure 10 . gate pull - down current ( i gatedn_slow ) vs. supply voltage (v cc ) 0 2 4 6 8 10 12 14 i gatedn_slow (ma) temper a ture ( c) 08931-012 v cc = 12v ?40 ?20 0 20 40 60 80 figure 11 . gate pull - d own current ( i gatedn_slow ) vs. temperature 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 0 5 10 15 20 25 i gatedn_slow (ma) v gate (v) 08931-013 figure 12 . gate pull - down current ( i g atedn_slow ) vs. gate voltage ( v gate ) ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 2 4 6 8 10 12 14 16 18 20 i gateup ( a) v cc (v) 08931-014 figure 13 . gate pull - u p current ( i gate up ) vs. supply voltage (v cc )
adm1275 rev. b | page 15 of 48 0 5 10 15 20 25 30 0 5 10 15 20 25 i gateup ( a) v gate (v) v cc = 12v v cc = 2.95v 08931-016 figure 14 . gate pull - u p current ( i gate up ) vs. gate voltage ( v gate ) ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 i gateup ( a) temper a ture (c) v cc = 12v 08931-015 ?40 ?20 0 20 40 60 80 figure 15 . gate pull - u p current ( i gate up ) vs. temperature 0 2 4 6 8 10 12 14 16 2 20 v gate (v) v cc (v) +85 c +25 c ?40 c 08931-017 4 6 8 10 12 14 16 18 figure 16 . gate drive voltage ( v gate ) vs. supply voltage ( v cc ), no l oad 0 2 4 6 8 10 12 14 16 v gate (v) v cc (v) 08931-018 2 4 6 8 10 12 14 16 18 20 +25c +85c ?40c figure 17 . gate drive voltage ( v gate ) vs. supply voltage (v cc ), 5 a l oad 0 2 4 6 8 10 12 14 16 ?40 ?20 0 20 40 60 v gate (v) temper a ture ( c) v cc = 12v v cc = 20v v cc = 2.95v 08931-019 80 figure 18 . gate drive voltage ( v gate ) vs. temperature, no l oad ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 ?40 i ss pull-u p ( a) temper a ture ( c) v cc = 12v 08931-020 ?20 0 20 40 60 80 figure 19 . soft start pull - u p current (i ss ) vs. temperature
adm1275 rev. b | page 16 of 48 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 i timerupflt (a) ?40 temper a ture ( c) 08931-021 ?20 0 20 40 60 80 v cc = 12v figure 20 . timer pull - u p c urrent , o vercurrent fault (i timerupflt ) vs. temperature ?20 0 20 40 60 80 ?10 ?8 ?6 ?4 ?2 0 i timeruppor ( a) ?40 temper a ture (c) v cc = 12v 08931-022 figure 21 . timer pull - u p c urrent , p ower- o n r eset (i timerup por ) vs. temperature ?40 ?20 0 20 40 60 80 0 1.5 3.0 4.5 i timerdnrt ( a) v cc = 12v temper a ture (c) 08931-023 figure 22 . timer pull - down c urrent , retry (i timer dn rt ) vs. temperature 0 100 200 300 400 500 600 700 800 900 1000 1 100 timer threshold (mv) ?40 temper a ture (c) 08931-024 ?20 0 20 40 60 80 low threshold (v cc = 12v) high threshold (v cc = 12v) figure 23 . timer t hresholds vs. temperature ?40 ?20 0 temper a ture ( c) 20 40 60 80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 foldback threshold (v) 2.95v 12v 20v 08931-025 figure 24 . foldb ack t hreshold vs. temperature 0 0.5 1.0 1.5 2.0 2.5 3.0 foldback hysteresis current ( a) 08931-026 2.95v 12v 20v ?40 ?20 0 temper a ture ( c) 20 40 60 80 figure 25 . foldback hysteresis current vs. temperature
adm1275 rev. b | page 17 of 48 0 20 40 60 80 100 120 140 160 180 200 220 240 foldback clam p (mv) temper a ture (c) 08931-027 v cc = 12v ?40 ?20 0 20 40 60 80 figure 26 . foldback clamp vs. temperature 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 2 20 oc response time (ns) v cc (v) 08931-128 4 6 8 10 12 14 16 18 +85c ?40c +25c figure 27 . severe overc urrent r esponse t im e vs. supply voltage (v cc ), v iset = 0.25 v 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 oc response time (ns) v cc (v) 08931-129 2 20 4 6 8 10 12 14 16 18 +85 c +25 c ?40 c figure 28 . severe overc urrent r esponse t ime vs. supply voltage (v cc ), v iset = 1 v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2 20 v cbos (mv) v cc (v) ?40 c 08931-130 +85 c +25 c 4 6 8 10 12 14 16 18 figure 29 . circuit breaker offset (v cbos ) vs. supply voltage (v cc ) 0 5 10 15 20 25 30 v sensecl (mv) temper a ture ( c) ?40 08931-131 ?20 0 20 40 60 80 v cc = 12v figure 30 . hot- swap sense voltage current li mit (v sensec l ) vs. temperature 0 5 10 15 20 25 30 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 v sensecl (mv) v flb (v) t a = 25 c 08931-132 figure 31 . hot- swap sense voltage current li mit (v sensec l ) vs. foldback voltage ( v flb )
adm1275 rev. b | page 18 of 48 0 5 10 15 20 25 30 35 40 45 50 v senseoc (mv) v cc (v) 08931-133 t a = 25 c 2 4 6 8 10 12 14 16 18 20 figure 32 . severe overc urrent voltage threshold (v senseoc ) vs. supply voltage (v cc ), v iset = v v cap 15 10 5 0 20 25 30 35 40 45 50 v senseoc (mv) v cc = 12v temper a ture ( c) 08931-144 ?40 ?20 0 20 40 60 80 figure 33 . severe overc urrent voltage threshold (v senseoc ) vs. temperature , v iset = v vcap 0 1 2 3 4 5 6 7 8 9 10 11 12 0 50 100 150 08931-134 i sensex (a) v sensex (v) figure 34 . sense +/sense ? i nput current ( i sensex ) vs. voltage ( v sense x ) 0 5 10 15 20 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 ?18 ?20 ?22 ?24 ?26 v gate (v) i gateup (a) v cc = 2.95v v cc = 12v v cc = 20v 08931-135 figure 35 . gate drive voltage (v gate ) vs. gate pull - u p current (i gate up ) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 1 2 3 4 5 6 7 8 9 10 v ol_pwrgd (v) i ol (ma) v cc = 2.95v v cc = 12v 08931-136 figure 36 . pwrgd pin, v o l_pwrgd vs. i ol 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 v ol (v) v cc = 2.95v v cc = 12v 08931-137 0 1 2 3 4 5 6 7 8 9 10 i ol (ma) figure 37 . latch and gpox/ alert x d igital o utput s, v ol vs. i ol
adm1275 rev. b | page 19 of 48 0 0.5 1.0 1.5 2.0 2.5 3.0 0 50 100 v vcap (v) i vcap ( a) +85 c +25 c ?40 c 08931-138 figure 38 . v cap voltage (v vcap ) vs. v cap load (i vcap ) 0 100 200 300 400 500 600 700 800 900 1000 1 100 1200 ?40 ?20 20 40 60 0 80 uv threshold (mv) temperature (c) v cc = 12v 08931-139 figure 39 . uv threshold ( uv th ) vs. temperature ?40 temper a ture (c) 0 100 200 300 400 500 600 700 800 900 1000 1 100 1200 ov threshold (mv) v cc = 12v 08931-140 ?20 20 40 60 0 80 figure 40 . ov threshold (ov th ) vs. temperature 0 0.5 1.0 1.5 2.0 2.5 3.0 ?25 ?20 ?15 ?10 ?5 0 5 v adr (v) i adr ( a) 00 decode 01 decode 10 decode 11 decode 08931-141 figure 41 . a dr pin voltage (v adr ) vs. current (i adr ) 08931-142 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 accurac y (%) sense vo lt age (mv) 16 averaging 128 averaging figure 42 . worst - case current sense power monitor error vs. current sense voltage (v sense ), 0c to 65c , v sense + = 12 v
adm1275 rev. b | page 20 of 48 functional block dia grams gate sense+ timer timer adm1275-1 gnd sense? vcc v cp 50 + ? vcap iout uv ov 1.0v 1.0v vout vout scl sda adr sense+ iout ldo charge pump timeout gpo2/alert2 pwrgd gpo1/alert1/conv latch current limit ss current limit flb iset timeout current limit control ref select 1.0v gate drive/ logic logic and pmbus ? + ? + ? + 08931-003 12-bit adc figure 43 . adm12 75 - 1 functional block diagram gate sense+ timer timer adm1275-2 gnd sense? vcc v cp vcap iout uv 1.0v vout scl sda adr sense+ iout ldo charge pump timeout pwrgd gpo1/alert1/conv current limit ss current limit flb iset timeout current limit control ref select 1.0v gate drive/ logic logic and pmbus 50 + + ? ? + ? 08931-004 12-bit adc figure 44 . adm1275 - 2 functional block diagram gate sense+ timer timer adm1275-3 gnd sense? vcc v cp vcap enable iout uv ov 1.0v 1.0v vout vout 12-bit adc scl sda adr sense+ iout ldo charge pump timeout gpo2/alert2 pwrgd latch current limit ss current limit flb iset timeout current limit control ref select 1.0v gate drive/ logic logic and pmbus 50 + + + + ? ? ? ? 08931-005 figure 45 . adm1275 - 3 functional block diagram
adm1275 rev. b | page 21 of 48 theory of operation when circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. these tra nsient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system. the adm1275 is designed to control the powering on and off of a system in a controlled manner, allowing a boar d to be removed from, or inserted into, a live backplane by protecting it from excess currents. the adm1275 can reside on the back - plane or on the removable board. powering the adm1275 a supply voltage from 2.95 v to 20 v is required to power the adm1275 via the vcc pin. the v cc pin pr ovides the majority of the bias current for the device ; the remainder of the current needed to control the gate drive and best regulate the v gs voltage is supplied by the sense+ pin. to ensure correct operation of the adm127 5 , the voltage on the vcc pin must be greater than or equal to the voltage on the sense+ pin. no sequencing of the vcc and sense+ rails is necessary. the sense+ pin can be as low as 2 v for normal operation provided that a voltage of at least 2.9 5 v is c onnected to the vcc pin. in most applications , both the v cc and sense+ pins are connected to the same voltage rail, but they are connected via separate traces to prevent accuracy loss in the sense voltage measurement (see figure 46). 2.95v to 20v r sense q 1 sense? gnd gate vcc sense+ adm1275 08931-028 figure 46 . powering the adm1275 to protect the adm1275 from unnecessar y reset s due to transient supply glitches , an external resistor and capacitor can be added , as shown in figure 47 . the values of these components should be chosen to provide a time constant that can filter any expected glitches. the resistor should , however , be small enough to keep voltage drop s due to quiescent current to a minimum. a supply decoupli ng capacitor should not be placed on the rail before the fet unless a resistor is used to limit the inrush current. 2.95v to 20v r sense q 1 sense? gnd gate vcc 330nf sense+ 22? adm1275 08931-029 figure 47 . transient g litch p rotection u sing an rc n etwork current sense i nputs the load current is monitored by measuring the voltage drop across an external sense resistor, r sense (see figure 48) . an internal current sense amplifier provides a gain of 50 to the voltage drop detected across r sense . the result is compared to an internal ref erence and used by the hot - swap control logic to detect when a n overcurrent condition occurs. r sense q 1 sense? gnd gate vcc sense+ adm1275 over- current reference 50 08931-030 + + ? ? figure 48 . hot - s wap current s ense a mplifier the sense inputs may be connected to multiple parallel sense resistors , which can affect th e voltage drop detected by the adm1275. the current flowing through the sense resistors creates an offset, resulting in reduced accuracy. to achieve better accuracy , averaging resistor s sum the current from the nodes of each sense resistor , as shown i n figure 49. t he t ypical value for the aver aging resistors is 10 . the value of the averaging resistors is chosen to be much greater than the trace resistance between the sense resistors terminals and the inputs to the adm1275. this greatly reduces the effects of differences in the trace resistances.
adm1275 rev. b | page 22 of 48 q 1 sense? gnd gate vcc sense+ bias current 2.95v to 20v 08931-031 figure 49 . connection of m ultiple s ense r esistors to the sense p ins current l imit r eference the current limit reference voltage determines the load current level to which the adm1275 limits the current during an overcurrent event. this refere nce voltage is compared to the gained - up current sense voltage to determine whether the limit is reached. an internal current limit reference selector block continuously compares the iset, s oft start, and f oldback voltages to determine which voltage is the lowest at any given time ; the lowest voltage is used as the current limit reference. this ensures that the programmed current limit, iset, is used in normal operation , and th at the s oft s tart and f oldback features reduce the current limit when required du ring st art up and/or fault conditions. r sense q 1 sense? gnd gate vcc iset ss flb sense+ adm1275 over- current 50 08931-032 figure 50 . current li mit r eference s election the foldback and soft start voltages vary during different modes of operation and are, therefore, clamped to minimum levels of 200 mv and 100 m v, respectively, to prevent zero current flow due to the current limit being too low. figure 51 provides an example of how the soft start, foldback, and iset vol tages interact during start up as the adm1275 is enhancing the fet and ch arging the load capacitances. depending on how the soft start and foldback features are configured, the hand - off point can vary to ensure that the fet is operated correctly. ss flb iset 1v 0.2v 0.1v v t current limit reference 08931-033 figure 51 . i nteraction of soft start, foldbac k, and is et current limits setting the c urrent l imit (iset) the maximum current limit is partially determined by selecting a sense resistor to match the current sense voltage limit on the controller for the desired load current. however, as currents become larger , the sense resistor requirements become smaller , and resolution can be difficult to achieve when selecting the appropriate sense resistor. the adm1275 provides an adjustable current sense voltage limit to handle this issue. the device allows the user to pro gram the required current sense voltage limit from 5 mv to 25 m v. the default value of 20 mv is achieved by connecting the iset pin directly to the vcap pin. this configures the device to use an internal 1 v reference, which equates to 20 mv at the sense i nputs ( see figure 52). adm1275 vcap iset c1 gnd 08931-034 figure 52 . fixed 20 mv current sense limit to program the sense voltage from 5 mv to 25 mv, a resistor divider is used to set a ref erence voltage on the iset pin ( see figure 53).
adm1275 rev. b | page 23 of 48 adm1275 gnd vcap iset c1 r1 r2 08931-035 figure 53 . adjustable 5 mv to 25 mv current sense limit the vcap pin has a 2. 7 v ( 1.5 %) internal generated voltage that can be used to set a voltage at the iset pin. assum ing that v iset equ als the voltag e on the iset pin, t he resistor divider should be sized to set the iset voltage as follows: v iset = v sense 50 w here v sense is the current sense voltage limit . the vcap rail can also be used as the pull - up supply for setting the i 2 c address. the vcap pin should not be used for any other purpose. to guarantee accuracy specifications , care should be taken not to load the vcap pin by more than 10 0 a. soft start a capacitor connected to the ss pin determines the inrush current profile. before the fet is enabl ed , the output voltage of the current limit reference selector block is clamped at 100 m v. this , in turn , holds the hot - swap sense voltage current limit , v sensecl , at approximately 2 mv. when the fet is requested to turn on, the ss pin is held at ground un til the voltage between the sense+ and sense? pins (v sense ) reaches the circuit breaker voltage, v c b . v cb = v sens ecl ? v cbos w here v cbos is typically 0.88 mv, making v cb = 1.12 mv. when the load current generates a sense voltage equal to v cb , a 10 a curre nt source is enabled , which charges the ss cap acitor and results in a linear ramping voltage on the ss pin. the current limit reference also ramps up accordingly , allowing the regulated load current to ramp up while avoiding sudden transients during power - up. the ss capacitor value is given by iset ss ss v t i c = where : i ss = 10 a. t = ss ramp tim e. for example, a 10 nf capacitor give s a soft start time of 1 ms. note that the ss voltage may intersect with the flb (foldback) voltage, and the current limi t reference may change to follow flb (see figure 51 ). this change has minimal impact on startup because the output voltage rises at a similar rate to the ss voltage. gate sense+ adm1275 gnd sense? 50 ss current limit flb iset timeout current limit control ref select 1.0v current limit vcap 10a gate drive/ logic + + ? ? 08931-036 v cp figure 54 . soft star t f oldback foldback is a method to active ly reduce the current limit as the voltage drop across the fet increases. it keeps the power across th e fet to a minimum during power - up, overcurrent, or short - circuit events. it also avoids the need to oversi ze the fet to accommodate worst - case conditions , resulting in board size and cost savings. the adm1275 detects the voltage drop across t he fet by looking at a resistor - divided version of the output voltage. it is assumed that the supply voltage remains constant a nd within tolerance. the device therefore relies on the principle that the drain of the fet is at the maximum expected supply voltage , and th at th e magnitude of the output voltage is relative to that of the v ds of the fet. using a resistor divider from the output voltage to the flb pin, a relationship from v out , and thus v ds , to v flb can be derived. the resistor divider should be designed to output a voltage equal to iset when v out falls below the desired level. this should be well below the working tolera nce of the supply rail. as v out continues to drop , the current limit reference follows v flb because it is now the lowest voltage input to the current limit reference selector block. this results in a reduction of the current limit and, therefore , the regul ated load current. t o prevent complete current flow restriction , a clamp becomes active when the current limit reference reaches 200 m v. t h e current limit cannot drop below this level . to suit the soa characteristics of a particular fet , the required minim um current for this clamp varies from design to design. however, the current limit reference fixes this clamp at 200 m v, which equates to 4 mv at the sense resistor. therefore, the main iset voltage can be adjusted to align this clamp to the required perce ntage current reduction . f or example, if iset equals 0. 8 v , the clamp can be set at 25% of the maximum current.
adm1275 rev. b | page 24 of 48 t imer the timer pin handles several timing functions with an external capacitor, c timer . the two comparator thresholds are v timer l (0.2 v) and v timer h (1 v). there are four timing current sources: a 3 a pull - up, a 60 a pull - up, a 2 a pul l - down, and a 100 a pull - down. these current and voltage levels, together with the value of c timer chosen by the user, determine the initial timing cycle time, the fault current limit time, and the hot - swap retry duty cycle. the timer capacitor value is determined using the following equation: c timer = ( t on 6 0 a)/ v timerh w here t on is the time th at th e fet is allowed to spend in regu - lation at the set current limit. the choice of fe t is based on matching this time with the soa requirements of the fet . foldback can be used to simplify the selection. when vcc is connected to the backplane supply, the internal supply of the adm1275 must be charged up. in a very short time , the internal supply is fully charged up and, because the undervoltage lockout (uvlo) voltage is exceeded at vcc, the device comes out of reset. during this first short reset period, the gate and timer pins are both held low. the adm1275 then goes through an initial tim ing cycle. the timer pin is pulled high with 3 a. when the timer reaches the v timerh threshold (1.0 v) , the first portion of the initial timing cycle is complete. the 100 a current source then pulls down the timer pin until it reaches v timerl (0.2 v). th e initial timing cycle duration is related to c timer by the following equation: a 100 ) ( a 3 ? + = timer timerl timerh timer timerh initial c v v c v t for example, a 100 nf capacitor results in a delay of approxi - mately 34 ms. if the uv and ov inputs indicate that the supply is within the defined window of operation when the initial timing cycle terminates, the device is ready to start a hot - swap operation. when the voltage across the sense resistor reaches the circu it breaker trip voltage, v cb , the 60 a timer pull - up current is activated , and the gate begins to regulate the current at the curre nt limit. this initiates a ramp - up on the timer pin. if the sense voltage falls below this circuit breaker trip voltage before the timer pin reaches v timerh , the 60 a pull - up is disabled and the 2 a pull - down is enabled. the circuit break er trip voltage is not the same as the hot - swap sense voltage current limit. there is a small circuit break er offset, v cbos , which means th at the timer actually starts a short time before the current reaches the defined current l imit. however, if the overcurrent condition is continuous and the sense voltage remains above the circuit breaker trip voltage, the 60 a pull - up remains active and the fet remains in regulation. this allows the timer pin to reach v timerh and initiate t he gate shutdown. on the adm1275 - 1 and adm1275 - 3, the latch pin is pulled low immediately. in latch - off mode, the timer pin is switche d to the 2 a pull - down when it reaches the v timerh threshold . the latch pin (adm1275 - 1 and adm1275 - 3) remains low. while the timer pin is being pulled down, the hot - swap controller is kept off and cannot be turned back on. when the voltage on the timer pin goes below the v timer l threshold, the hot - swap controller can be reenabled by toggl ing the uv pin or by using the pmbus operation command to toggle the on bit from on to off a nd then on again . hot - swap retry duty cycle the adm1275 - 1 and adm1275 - 3 turn off the fet after an overcurrent fault and then use the capacitor on the timer pin to p rovide a delay before automatically retrying the hot - swap operation . to configure the adm1275 - 1 and adm1275 - 3 for auto retry mode , the latch pin is tied to the uv pin or to the enabl e pin (adm1275 - 3 only). note that a pull - up is required o n the latch pin . when an overcurrent fault occurs , the timer capacitor is charged with a 60 a pull - up current. when the timer pin reaches v timerh , the gate pin is pulled down. when the latch pin is tied to the uv pin or the enable pin for a uto retry mode, the timer pin is pulled down wit h a 2 a current sink. when the timer pin reaches v timerl (0.2 v), it automatically restarts the hot - swap operation. the duty cycle of this automatic retry cycle is set by the ratio of 2 a/60 a, which approximates to being on about 4 % of the time. the v alue of the timer capacitor determines the on time of this cycle , which is calculated as follows: t on = v timerh ( c timer /60 a ) t off = ( v timerh ? v timer l ) ( c timer / 2 a ) a 100 nf timer cap acitor gives an on time of 1.67 ms and an off time of 40 ms . the d evice retr ies in de finitely in this manner and can be disabled manually by holding the uv or enable pin low or by disconnecting the latch pin. to prevent thermal stress, an rc network can be used to extend the retry time to any desired lev el. fet gate drive clamp s the charge pump used on the gate pin is capable of driving the pin to v cc + (2 v cc ), but it is clamped to less than 14 v above the sense pins and less than 31 v. these clamps ensure that the maximum v gs rating of the fet is not exceeded .
adm1275 rev. b | page 25 of 48 fast response to sev ere o v ercurrent the adm1275 features a separate high bandwidth current sense amplifier that is used to detect a severe overcurrent that is indicative of a short - circuit condition. a fast response time allows the adm1275 to ha ndle events of this type that could otherwise cause catastrophic damage if not detected and acted on very quickly. the fast response circuit ensures th at th e adm1275 can detect an overcurrent event at approx imately 200 % to 250% of the normal current limit (iset) and can respond to and control the current within 1 s, in most cases. u ndervoltage and over voltage the adm1275 monitors the supply voltage for undervoltage (uv) and overvoltage (ov) conditions. the uv and ov pins are connected to the input of an in ternal voltage comparator, and its voltage level is internally compared with a 1 v voltage reference. figure 55 illustrates the voltage monitoring input connections. an external resistor network divides the supply voltage for moni toring. an undervoltage event is detected when the voltage connected to the uv pin falls below 1 v , and the gate is shut down using the 10 ma pull - down device. similarly, when an overvoltage event occurs and the voltage on the ov pin exceeds 1 v , the gate is shut down using the 10 ma pull - down device. gate sense+ adm1275 gnd sense? gate drive r sense q1 v in 1v 1v iout uv ov vcc 08931-037 50 + ? ? + + ? figure 55 . undervoltage and overvoltage s upply m onitoring enable input (adm1275 - 3 only) the adm1275 - 3 provides a dedicated enable digital input pin instead of the gpo1/ alert1 /conv pin on the adm1275 - 1 and the adm1275 - 2 . the enable pin allows the adm1275 - 3 to be kept off using a hardware signal, even when the volta ge on the uv pin is above 1.0 v and the voltage on the ov pin is less than 1.0 v. although the uv pin can be used to provide a digital enable signal, using the enable pin for this purpose means that the ability to monitor for under voltage conditions is not lost. in addition to the conditions for the uv and ov pins, the adm1275 - 3 enable input pin must be high for the dev ice to begin a power - up sequence. if an enable function is required on the adm1275 - 1 or adm1275 - 2, which do not have a dedicated enable pin, a similar function can be achieved using the uv pin directly. alternatively, if the uv divider funct ion is still required, the configuration shown in figure 56 can be used. v in r1 d1 r2 en uv system control adm1275 08931-038 figure 56 . u sing the uv pin as an e nable diode d1 prevents the external driver pull - up from affecting the uv threshold. select di ode d1 using the following criteria: ( v f d1 ) + ( v ol en ) << 1.0 v ( i f = v in / r1 ) make sure that the en sink current does not exceed the specified v ol value. if the open - drain device has no pull - up, the diode is not required. power good the pwrgd output c an be used to indicate whether the output voltage is above a user - defined threshold and can , therefore , be considered good. the pwrgd output is derived using the flb resistor network, composed of r1 and r2 ( see figu re 57 ). pwrgd is an open - drain output that pulls low when the voltage at the flb pin is lower than 1.1 v iset (power bad). when the voltage at the flb pin is above this threshold (indicating th at th e output voltage is up), the open - drain pull - down is dis abled, allowing pwrgd to be pulled high. pwrgd is guaranteed to be in a valid state for v cc 1 v . h ysteresi s on the flb pin is provided by a 2 a internal current source that is switched o n when the v flb input voltage exceeds the input threshold. the current source is disconnected when v out drops below the foldback threshold voltage minus the hysteresis voltage. resistor r3 is internal to the adm1275. the hysteresis voltage at the flb pin can be varied by adjusting the parallel combination of resistor r1 and r esistor r2. v out flb 2a r1 r2 r3 pwrgd 1.3k switch is on when comparator output is high 1.1 v iset 08931-039 figure 57 . g eneration of pwrgd s ignal
adm1275 rev. b | page 26 of 48 vout mea surement the vout pin on the adm1275 - 1 and adm1275 - 3 can be used to provide an alternate voltage for the power monitor to measure. the user can choose to measure the voltage at the sense+ pin or the voltage at the vout pin, using either the low or high inp ut voltage range . if the vout pin will be used to measure the output voltage after the f e t, a 1 k? resistor should be inserted in series between the source of the fet and the vout pin. this resistor provide s some separation between the adm1275 and the fet source during a fault condition, so that adm1275 operation is not affected. fet health the adm1275 provides a method of detecting a shorted pass fet. the fet health status can be used to generate an alert on the gpo1/ alert1 /conv and gpo2/ alert2 pins. by default at power - up , an alert is generated on the gpo2/ alert2 pin of the adm1275 - 1 and adm1275 - 3 i f the fet health status indicates that a bad fet is present. fet health is considered bad if all of the fo llowing conditions are true: ? the adm1275 is holding the fet off, for example, during the initial power - on cycle time. ? v sense > 2 mv . ? v gate < ~1 v , that is, less than the fet gate threshold . power monitor the adm1275 features an integrated adc that is used to accurately measure the current sense voltage and either the input or output voltage. because t he adm1275 - 1 and adm1275 - 3 have a vout pin , the power monitor can be configured using the pmbus to measure either the input or the output voltage . the adm1275 - 2 does not have a vout pin, so only the input voltage at the sense+ pin can be measured. the adm1275 can report the measured current and either the input or output voltage. the peak_iout, peak_vin, and peak_vout commands can be used to read the highest pea k current or voltage since the value was last cleared. an averaging function is provided for voltage and current that allows a number of samples to be averaged by the adm1275. this function re duc es the need for postprocessing of sampled data by the host pr ocessor. the number of samples that can be averaged is 2 n , where n is in the range of 0 to 7. the power monitor current sense amplifier is bipolar and can measure both positive and negative currents. the power monitor amplifier has an input range of 25 mv . two input voltage ranges are available and can be selected using the pmbus interface: 0 v to 6 v (low input range) and 0 v to 20 v (high input range) . the two basic modes of operation for the power monitor are single shot and continuous. in single - shot m ode , the power monitor sample s the input voltage and current a number of times, depending on the averaging value selected by the user. the adm1275 returns a single value corresponding to the average voltage and current measured. when configured for continu ous mode, the power monitor continuously sample s voltage and current, making the most recent sample available to be read. the single - shot mode can be triggered in a number of ways. the simplest is by selecting the single - shot mode using the pmon_config co mmand and writing the convert bit using the pmon_control command. the convert bit can also be written as part of a pmbus group command. using a group command allows multiple devices to be written to as part of the same i 2 c bus transaction, with all devices executing the command when the stop condition appears on the bus. in this way , several devices can be triggered to sample at the same time. when the gpo1/ a l er t 1 /conv pin is set to the convert ( conv ) mode, an external hardware signal can be used to trigger the single - shot sampling of one or more parts at the same time .
adm1275 rev. b | page 27 of 48 pmb us interface the i 2 c bus is a common, simple serial bus used by many devices to communicate. it defines the electrical specifications, the bus timing , the physical la yer , a nd some basic protocol rules. smbus is based on i 2 c and aims to provide a more robust and fault - tolerant bus. functions such as bus timeout and packet error checking are added to help achieve this robustness , along with more specific definitions of t he bus messages used to read and write data to devices on the bus. pmbus is layered on top of smbus and , in turn , on i 2 c . u sing the smbus defined bus messages , pmbus defines a set of standard commands that can be used to control a device that is part of a power chain. the adm1275 command set is based upon the pmbus ? power system management protocol specification, part i and part ii, re vision 1.1. this version of the standard is intended to provide a common set of commands for communicating with dc - to - dc type devices. however, many of the standard pmbus commands can be mapped directly to the functions of a hot - swap controller. part i and part ii of the pmbus standard describe the basic commands and how they can be used in a typical pmbus setup. the following sections describe how the pmbus standard and the adm1275 sp ecific commands are used. device addressing t he adm1275 is available in three models : the adm1275 - 1, the adm1275 - 2 , and the adm1275 - 3 . the pmbus address is 7 bits in size. the upper 5 bits (msbs) of the address word are fixed and are different for each mod el , as follows: ? adm1275 - 1 : base a ddress is 00100xx ( 0x10 ) ? adm1275 - 2 : base address is 00110xx ( 0x18 ) ? adm1275 - 3 : base address is 01000xx ( 0x20 ) the adm1275 - 1, adm1275 - 2, and adm1275 - 3 all have a single adr pin that is used to select one of four possible addr esses for a given model. the adr pin connection selects the lowest two bits (lsbs) of the 7 - bit address word (see table 8 ) . table 8 . pmbus addresses and adr pin connection value of address l sbs adr pin connection 00 connect to gnd 01 150 k? resistor to gnd 10 no connection (floating) 11 connect to vcap smb us protocol usage all i 2 c transactions on the adm1275 are done using smb us defined bus protocols. the following smbus protocols ar e implemented by the adm1275: ? send b yte ? receive b yte ? write b yte ? read b yte ? write w ord ? read w ord ? block r ead p acket error checking the adm1275 pmbus interface supports the use of the p acket e rror c hecking (pec ) byte that is defined in the smbus standard. th e pec byte is transmitted by the adm1275 during a read transaction or sent by the bus host to the adm1275 during a write transaction. the adm1275 supports the use of pec with all the smbus protocols that it implements. the use of the pec byte is optional. t h e bus host can decide whether to use the pec byte with the adm1275 on a message - by - message basis. there is no need t o enable or disable pec in the adm1275. the pec byte is used by the bus host or the adm1275 to detect errors during a bus transaction , depen ding on whether the trans - action is a read or a write. if the host determines that the pec byte read during a read transaction is incorrect, it can decide to repeat the read if necessary. if the adm1275 determines that the pec byte sent during a write tran saction is incorrect, it ignore s the command ( does n ot execute it ) and sets a status flag . within a group command, the host can choose to send or not send a pec byte as part of the message to the adm1275.
adm1275 rev. b | page 28 of 48 smb us message formats figure 58 to figure 65 show all the smbus protocols supported by the adm1275, along with the pec variant. in these figures, unshaded cells indicate th at the bus host is actively driving the bus ; shad ed cells indicate that the adm1275 is driving the bus. figure 58 to figure 65 use the following abbreviations: s = start condition sr = repeated start condition p = stop condition r = read bit w = write bit a = acknowledge bit (0) a = acknowledge bit (1) a represent s the ack ( acknowledge ) bit. the ack bit is typi - cally active low (logic 0) if the transmitted byte is successfully received by a device. however, when the receiving device is the bus master, the acknowledge bit for the last byte read is a logic 1, indicated by a . s p a a w sla ve address dat a byte s p a a w sla ve address dat a byte pec a master t o sl a ve sla ve t o master 08931-040 figure 58 . send byte and send byte with pec s p a a r sla ve address dat a byte s p a a r sla ve address dat a byte pec master t o sl a ve sla ve t o master 08931-041 a figure 59 . receive byte and receive byte with pec s a a w sla ve address command code dat a byte p a s a a w sla ve address command code dat a byte p a pec a master t o sl a ve sla ve t o master 08931-042 figure 60 . write byte and write byte with pec a sla ve address r dat a byte sr a a s a a w sla ve address command code p a pec s a a w sla ve address command code sla ve address p r dat a byte sr a master t o sl a ve sla ve t o master 08931-043 figure 61 . read byte and read byte with pec p s a a w sla ve address command code dat a byte low a a s a a w sla ve address command code dat a byte low a dat a byte high dat a byte high a p a pec master t o sl a ve sla ve t o master 08931-044 figure 62 . write word and write word with pec sr a sla ve address a r s a w sla ve address command code a dat a byte low p a a a dat a byte high sr a sla ve address a r s a w sla ve address command code a dat a byte low dat a byte high p pec master t o sl a ve sla ve t o master 08931-045 figure 63 . read word and read word with pec
adm1275 rev. b | page 29 of 48 sr a sla ve address a r s a w sla ve address command code a byte count = n a dat a byte 1 p dat a byte n a dat a byte 2 sr a sla ve address a r s a w sla ve address command code a byte count = n a dat a byte 1 a dat a byte n p pec a dat a byte 2 master t o sl a ve sla ve t o master 08931-046 a a figure 64 . block read and b lock read with pec master t o sl a ve sla ve t o master a low d at a byte a s a w device 1 address command code 1 a high d at a byte one or more d at a bytes a low d at a byte a sr a w device 2 address command code 2 a high d at a byte one or more d at a bytes a low d at a byte a sr a w device n address command code n a p high d at a byte one or more d at a bytes 08931-047 master t o sl a ve sla ve t o master a pec 1 p a low d at a byte a s a w device 1 address command code 1 a high d at a byte one or more d at a bytes a pec 2 a low d at a byte a sr a w device 2 address command code 2 a high d at a byte one or more d at a bytes a pec n a low d at a byte a sr a w device n address command code n a high d at a byte one or more d at a bytes 08931-048 figure 65 . group command and group command with pec gr oup c o mmands the pmbus standard define s what are known as g roup c ommands . group commands are single bus transactions that send commands or data to more than one device at the same time. each device is addressed separately, using its own address ; there is no special group command address. a gro up command transaction can contain only write commands that send data to a device. it is not possible to use a group command to read data from devices. from an i 2 c protocol point of view, a normal write command consists of the following : ? i 2 c start conditio n ? slave address bits and a write bit (followed by ack from the slave device) ? one or more data bytes (e ach of which is followed by ack from the slave device ) ? i 2 c stop condition to end the transaction a group command differs from a nongroup command in that after the data is written to one slave device, a repeated start condition is put on the bus followed by the address of the next slave device and data. this continues until all the devices have been written to, at which point the stop condition is put on t he bus by the master device. the format of a group command and a group command with pec is shown in figure 65. each device that is written to as part of the group command does not immediately execute the command written. the devic e must wait until the stop condition appears on the bus. at that point , all devices execute their commands at the same time. using a group command, it is possible, for example, t o t urn multiple pmbus devices on or off at the same time. in the case of the a dm1275 , it is also possible to issue a p ower m onitor command that initiates a conversion, causing multiple adm1275 devices to sample together at the same time . this is analogous to connecting the gpo1/ alert1 /conv pins together and configu ring the pin in the conv ert (conv) mode to drive the power monitor sampling.
adm1275 rev. b | page 30 of 48 hot - swap c ontrol commands operation command the gate pin that drives the fet is controlled by a dedicated hot - swap state machine. the uv and ov input pins, along with the timer an d ss pins and the current sense , all feed into the state machine and control when and how strongly the gate is turned off. it is also possible to control the hot - swap gate output using commands over the pmbus interface. the operation com - mand can be used t o request the hot - swap output to turn on. however, if the uv pin indicates that the input supply is less than required, the hot - swap output is not turned on, even if the operation command indicates that the output should be enabled. if the operation comman d is used to disable the hot - swap output , the gate pin is held low, even if all hot - swap state machine control inputs indicate that it can be enabled. the default state of the operation command on bit is 1, so the hot - swap output is always enabled when th e adm1275 comes out of uvlo. if the on bit is never changed, the uv input ( or the enable input on the adm1275 - 3 ) is the hot - swap master on / off control signal. by default at power - up , the operation command is disabled and must be enabled using the device_co nfig command. this prevent s inadvertent shutdowns of the hot - swap controller by software. if the on bit is set to 0 while the uv signal is high , the hot - swap output is turned off. if the uv signal is low or if the ov signal is high, the hot - swap output wi ll already be off and the status of the on bit has no effect. if the on bit is set to 1, the hot - swap output is requested to turn on. if the uv signal is low or if the ov signal is high , setting the on bit to 1 has no ef fect, and the hot - swap output remai n s off. it is possible to determine at any time whether the hot - swap output is enabled using the status_byte or the status_word command (see the status commands section ) . the operation command can also be used to c lear any latched faults in the status registers. to clear latched faults, set the on bit to 0 and then reset it to 1. device_config command th e device_config command is used to configure cert ain settings within the adm1275, f or example, to enable or disabl e foldback in the hot - swap controller or to modify the duration of the severe overcurrent glitch filter. this command is also used to configure the polarity of th e second iout current warnings. at power - up , the operation command is disabled and the adm127 5 responds with a nack if the operation command is received. to allow use of the operation command , the operation_cmd_en bit must be set using the device_config command. power_cycle command the power_cycle command can be used to request th at th e adm1275 b e turn ed off for ~4 seconds and then back on. this command can be useful if the processor that controls the adm1275 is also powered off when the adm1275 is turned off. this command allows the processor to request th at th e adm1275 turn off and back on again as part of a single command. adm1275 information commands capability command th e capability command can be used by host processors to determine the i 2 c bus features supported by the adm1275. the features reported are the maximum bus speed and whether the device supports the p acket e rror c hecking ( pec ) byte and the smbalert reporting function. pmbus_revision command th e pmbus_revision command reports the version of part i and part ii of the pmbus standard. mfr_id, mfr_model , and mfr_revision commands the m fr_id, mfr_model, and mfr_revision commands return ascii strings that can be used to facilitate detection and identification of the adm1275 on the bus. these commands are read using the smbus b lock read message type. this message type requires that the adm 1275 return a byte count corresponding to the length of the string data that is to be read back. status commands the adm1275 provides a number of status bits that are used to report faults and warnings from the hot - swap controller and the power monitor. t hese status bits are located in six different registers that are arranged in a hierarchy. the status_byte and status_word commands provide 8 bits and 16 bits of high level information , respectively . the status_byte and status_word commands contain the most imp ortant status bits, as well as pointer bits that indicate whether any o f the four other status registers need to be read for more detailed status information. in the adm1275 , a particular distinction is made between faults and warnings. a fault is alwa ys generated by the hot - swap controller and is defined by hardware component values . t hree events can ge nerate a fault : ? o verc urrent condition that caus es the hot - swap timer to time out ? o ver volt age condition on the ov pin ? u nder voltage condition on the uv pi n when a fault occurs, the hot - swap controller always take s some action, usually t o t urn off the gate pin , which is driving the f e t. a fault can also generate a n smbalert on one or both of the gpox/ alertx pins.
adm1275 rev. b | page 31 of 48 all warnings in the adm1275 are generated by the p ower m onitor sampling voltage and current and then comparing these measurements to the threshold values set by the various limit commands. a warning has no effect on the hot - swap controller, but it may generate a n smbalert on one or both of the gpox/ alertx output pins. when a status bit is set, it always means that the status condition fault or warning is active or was active at some point in the past. when a fault or warning bit is set, it is latched until it is exp licitly cleared using ei ther the operation or the clear_fault s command. some other status bits are live, that is, they al ways reflect a status condition and are never latched. status_byte and status_word commands the status_byte and status_word commands ca n be used to obtain a snap shot of the overall part status. these commands indicate whether it is necessary to read more detailed information using the other status commands. the low byte of the word returned by the status_word command is the same byte ret urned by the status_byte command. the high byte of the word returned by the status_word command provides a number of bits that can be used to determine which of the other status commands needs to be issued to obtain all active status bits. status_input com mand the status_ input command r eturns a number of bits relating to voltage faults and warnings on the input supply. status_vout command the status_ vout command returns a number of bits relating to voltage faults and warnings on the output supply. this comm and is not available on the adm1275 - 2. status_iout command the status_ iout command returns a number of bits relating to current faults and warnings on the output supply. status_mfr_specific command th e status _mfr _ specific command is a standard pmbus comman d, but the contents of the byte returned is specific to the adm1275. clear_faults command the clear_faults command is used to clear fault and warnings bi ts when they are set. fault and warnings bits are latched when they are set . in this way, a host can re ad the bits any time after the fault or warning condition occurs and determine which problem actually occurred. if the clear_faults command is issued and the fault or warning condition is no longer active, the status bit is cleared. if the conditio n is st ill active for example , if an i nput voltage is below the under v oltage threshold of the uv pin the clear_faults command attemp ts to clear the status bit, but that status bit is immediately set again. gpo and a lert pin setup commands two multi purpose pins a re provided on the adm1275 - 1 : gpo1/ alert1 /conv and gpo2/ alert2 . one multi - purpose pin is provided on the adm1275 - 2 (gpo1/ alert1 / conv), and on the adm1275 - 3 (gpo2/ alert2 ) . the gpo1/ alert1 /conv and gpo2/ alert2 pins have two output modes of operation. these pins can be configured indepen - dently over the pmbus as general - purpose digital outputs. they can both be configured to generate a n smbalert when o ne or more fault/warning status bits become active in the pmbus status registers. for a n example of how to configure these pins to generate an smbalert and how to respond and clear the condition , see the example use of smb us alert response address section. the gpo1/ alert1 /conv pin can also be configured as an input (conv) to drive the po wer monitor in single - shot run mode and to control when a power monitor adc sampling cycle begins . this function can be used to synchronize sampling across multiple adm1275 devices , if required. alert1 _ config and alert2_ config commands using combinations of bit masks, the alert1_config and alert2_config commands can be used to select the status bits that, when set, g enerate a n smbalert signal to a processor. they can also be used to set a gpo mode on the pin, so that it is under software control. if this mode is set, the smb alert masking bits are ignored. on the adm1275 - 1, one of the input s can also be configured as a hardware - based convert control signal. if th is mode is set, the gpo and smbalert masking bits are ignored. power monitor comman ds the adm1275 provides a high accuracy , 12- bit current and voltage power monitor. the power monitor can be configured in a num ber of different modes of operation and can run in either continuous mode or single - shot mode with a number of different sample averaging options. pmon_ config command the power monitor can run in a number of differ ent modes with different input voltage ra nge settings. the pmon_config c ommand is used to set up the power monitor. the settings that can be configured are as follows : ? single - shot or c ontinuous sampling ? vin or vout sampling ( no vout sampling for the adm1275 - 2) ? voltage input range ? current and v ol tage sample averaging modifying the power monitor settings while the power monitor is sampling is not supported. the power monitor must be stopped before any of these settings are changed to ensure correct operation and avoid any potential spurious data an d status alerts being generated.
adm1275 rev. b | page 32 of 48 pmon_ control command p ower monitor sampling can be initiated via software or via hardware , as follows : ? pmon_control command . this command can be used with single - shot or continuous mode. ? gpo1/ alert1 /conv p in. if this pin is configured for convert mode, an external hardware signal can be used to take this pin high, triggering the single - shot sampling of one or more parts together. read_vin, read_ vout , and read_ iout commands the adm1275 power monitor measures the voltage developed across the sense resistor to provide a current measurement. on the adm1275 - 1 and adm1275 - 3, the user can choose to measure either the input voltage from the sense+ pin or the output voltage present on the vout pin. the adm1275 - 2 can measure only the input voltage from the sense+ pin . peak_iout, peak_vin, and peak_ vout commands in addition to the standard pmbus commands for reading voltage and current, the adm1275 provides commands that can report the maximum peak voltage or current sa mple since the peak value was last cleared. the peak values are updated only after the power monitor has sampled and averaged the current and voltage measurements. individual peak values are cleared by writing a 0 value with the corresponding command. warn ing limit setup comm ands the adm1275 power monitor can monitor a number of differ - ent warning conditions simultaneously and report any current or voltage values that exceed the user - defined thresholds using the status commands. all comparisons performed by the power monitor require the measured voltage or current value to be strictly greater or less than the threshold value. at power - up, all threshold limits are set to either minimum scale (for undervoltage or under curre nt conditions) or to maximum scale (f or over voltage or over current conditions) . this effectively disables the generation of any status warnings by default ; warning bits are not set in the status registers until the user explicitly sets the thre shold values. vin_ov_warn_ limit and vin_uv_warn_ l imit commands the vin_ov_warn_limit and vin_uv_warn_limit commands are u sed to set the ov and uv thresholds on the input voltage, as measured at the sense+ pin. vout_ov_warn_limit and vout_uv_warn_ limit commands the vout_ov_warn_limit and vout_uv_warn_ lim it commands are used to set the ov and uv thresholds on the output voltage, as measured at the vout pin on the adm1275 - 1 and adm1275 - 3. iout_oc_warn_ limit command the iout_oc_warn_limit command is used to set the oc threshold for the current flowing throu gh the sense resistor. iout_warn2_ limit command the iout_warn2_limit command provides a second current warning threshold that can be programmed. the polarity of this warning can be set to overcurrent or under current using the device_config command. pmb us d irect format convers ion the adm1275 uses the pmbus direct format to represent real - wo rld quantities such as voltage and current values. a direct format number takes the form of a 2 - byte, twos complement, binary integer value. it is possible to convert betw een direct format value and real - world quantities using the following equations. equation 1 converts from real - world quantities to pmbus direct values, and equation 2 converts pmbus direct format values to real - world values. y = ( mx + b ) 10 r (1) x = 1/ m ( y 10 ?r ? b ) (2) where: y is the value in pmbus direct format. x is the real - world value. m is the slope coefficient, a 2 - byte, twos complement integer . b is the offset , a 2 - byte, twos complement integer . r is a scaling exponent , a 1 - byte, twos complement inte ger . the same equations are used for voltage and current conversions, the only difference being the values of the m, b, and r coefficients that are used. table 9 lists all the coefficients required for the adm1275 . the current coefficients shown are dependent on the value of the external sense resistor used in a given application. this means that an additional calculation must be performed to take the sense resistor value into account to obtain the coefficients for a specific sense resistor value . the sense resistor value used in the calculations to obtain the coefficients is expressed in milliohms. the m coefficients are defined as 2 - byte twos complement numbers in the pmbus standard, therefore the maximum positi ve value that can be represented is 32767. if the m value is greater than that, and is to be stored in pmbus standard form, then the m coefficients should be divided by 10, and the r coefficient increased by a value of 1. for example, if on the 20 v range, a 10 milliohm sense resistor is used, the m coefficient is 6043, and the r coefficient is ? 1.
adm1275 rev. b | page 33 of 48 table 9 . pmbus conversion to real - world coefficients coefficient current (a) voltage (v) 0 v to 6 v range 0 v to 20 v range m 807 r sense 6720 19,199 b 20,475 0 0 r ?1 ?1 ?2 example 1 iout_oc_warn_limit requires a current - limit value expressed in direct format. if the required current limit is 10 a, and the sense resistor is 2 m, then the first step is to determine the voltage coefficient. this is simply m = 807 2, giving 1614. using equation 1 and expressing x, in units of amps y = ((1614 10) + 20,475) 10 ?1 y = 3661.5 = 3662 (rounded up to integer form) writing a value of 3662 with the iout_oc_warn_limit command sets an o vercurrent warning at 10 a. example 2 the read_iout command returns a direct format value of 3339 representing the current flowing through a sense resistor of 1 m?. to convert this value to the current flowing, use equation 2, with m = 807 1. x = 1/807 (3339 10 1 ? 20,475) x = 16.00 a this means that when read_iout returns a value of 3339, 16.00 a is flowing in the sense resistor. voltage and current conversion u sing lsb values the direct format voltage and current values returned by the read_vin, rea d_vout, read_iout commands, and the corresponding peak versions, are actually the data outpu t directly by the adm1275 adc. as the voltages and currents are really a 12 - bit adc output code, they can also be converted to real - world values with knowledge of the size of the lsb on the adc. the m, b, r coefficients defined for the pmbus conversion are required to be whole integers by the standard, and have therefore been rounded - off slightly. using this alternative method, with the exact lsb values, can provi de slightly more accurate numerical conversions. to convert an adc code to current in amperes, the following formulas can be used: v sense = lsb 25mv ( i adc ? 2048) i out = v sense /( r sense 0.001) where: v sense = (v sense+ ) ? (v sense? ). lsb 25mv = 12.4 v. i a dc is the 12 - bit adc code. i out is the measured current value in amperes. r sense is the value of the sense resistor in milliohms. to convert an adc code to a voltage, the following formula can be used: v m = lsb xv ( v adc + 0.5) where: v m is the measured va lue in volts. v adc is the 12 - bit adc code. lsb xv values are based on the voltage range (see table 10). table 10 . voltage ranges and lsb values voltage range, lsb xv lsb magnitude 0 v to 6 v 1.488 mv 0 v to 20 v 5.208 mv to convert a current in amperes to a 12 - bit value, the following formula can be used (round the result to the nearest integer): v sense = i a r sense 0.001 i code = 2048 + ( v sense / lsb 25mv ) where: v sense = (v sense+ ) ? (v sense ? ). i a is the current value in amperes. r sense is the value of the sense resistor in milliohms. i code is the 12 - bit adc code. lsb 25mv = 12.4 v. to convert a voltage to a 12 - bit value, the following formula can be used (round the result to the nearest inte ger): v code = ( v a / lsb xv ) ? 0.5 where: v code is the 12 - bit adc code. v a is the voltage value in volts. lsb xv values are based on the voltage range (see table 10).
adm1275 rev. b | page 34 of 48 adm1275 alert pin be havio r the adm1275 provides a very flexible alert system, whereby one or more fault/warning conditions can be indicated to an external device. faults and warnings a pmbus fault on the adm1275 is always generated due to an analog event and causes a change in state in the hot - swap outpu t, turning it off. the three defined fault sources are as follows : ? u nder voltage (uv) event detected on the uv pin ? o vervoltage (ov) event detected on the ov pin ? over current (oc) event that causes a hot - swap timeout f aults are continuously monitored, and, as long as power is applied to the device, they cannot be disabled. when a fault occurs, a corresponding status bit is set in one or more status_ xxx registers. a value of 1 in a status register bit field always indicate s a fault or warning condition. fault a nd warning bits in the status registers are latched when set to 1. to clear a latched bit to 0 provided that the fault condition is no longer active use the clear_faults command or use the operation command to turn the hot - swap output off and then on again . a warni ng is less severe than a fault and never causes a change in the state of the hot - swap controller . the eight sources of a warning are defined as follows : ? cml : a communications error occurred on the i 2 c bus ? hs t imer was a ctive (hsta) : t he current re gulation was active, but does no t n ecessarily shut the system down ? iout oc w arning from the adc ? iout w arning 2 from the adc ? vin uv w arning from the adc ? vin ov w arning from the adc ? vout uv w arning from the adc ( adm1275 - 1 and adm1275 - 3 only) ? vout ov warning from the adc (adm1275 - 1 and adm1275 - 3 only ) generating an alert a host device can periodically poll the adm1275 using the status commands to determine whether a fault/warning is active. however, this polling is very inefficient in terms of software and pro cessor resources. the adm1275 has gpox/ alertx output pins that can be used to generate interrupts to a host processor . ? adm1275 - 1 : gpo1/ alert1 /conv and gpo2/ alert2 ? adm1275 - 2 : gpo1/ alert1 /conv ? adm1275 - 3 : gpo2/ alert2 by default at power - up, the open - drain gpox/ alertx outputs are high impedance , so the pin s can be pulled high through resistor s . no faults or warnings are enabled on the gpo1/ alert1 /conv pin at power - up ; the user must explicitly enable the faults or warnings to be monitored. the fet h ealth b ad warning is active by default on the gpo2/ alert2 pin at power - up. any one or more of the faults and warnings lis ted in the faults and warnings section can be enabled and cause an alert, making the corresponding gpox/ alertx pin active. by default, the active state of a gpox/ alertx pin is lo w. for example, to use gpo1/ alert1 /conv to monitor the vout uv warning from the adc, the followings steps must be performed: 1. set a threshold level with the vout_uv_warn_limit command . 2. start the power monitor sampling on vout . if a vout sa mple is taken that is below the configured vout uv value, the gpo1/ alert1 /conv pin is taken low, signaling an interrupt to a processor. handling/clearing an alert when faults/warnings are configured on the gpox/ alertx p ins, the pins become active to signal an interrupt to the processor. (these pins are active low, unless inversion is enabled .) the gpox/ alertx signal function s as an smbalert. note that the gpox/ alertx pins can become ac tive indepen - dently of each other, but they are always made inactive together. a processor can respond to the interrupt in one of two basic ways: ? if there is only one device on the bus, the processor can simply read the status bytes and issue a clear_fault s command to clear all the status bits , which causes the deassertion of the gpox/ alertx line. if there is a persistent fault for example, an undervoltage on the input the status bits remain set after the clear_faults command is executed b ecause the fault has not been removed. however, the gpox/ alertx line is not pulled low unless a new fault/ warning becomes active. if the cause of the smbalert is a power monitor generated warning and the power monitor is running continuo usly, the next sample generate s a new smbalert after the clear_faults command is issued . ? i f there are several devices on the bus, the processor can i ssue an smbus a lert r esponse a ddress command to find out which device asserted the smbalert line. the proce ssor can read th e status bytes from that device and issue a clear_faults command .
adm1275 rev. b | page 35 of 48 smb us alert response addre ss the smbus a lert r esponse a ddress (ara) is a special address that can be used by the bus host to locate any devices that need to talk to it. a ho st typically use s a hardware interrupt pin to monitor the smbus alert pins of a number of devices. when the host interrupt occurs, the host issues a message on the bus using the smbus r eceive b yte or r eceive byte with pec protocol. the special address used by the host is 0x0c. any device s that have an smbalert signal return their own 7 - bit address as the seven msbs of the data byte. the lsb value is not used and can be either 1 or 0. the host reads the device address from the received data byte and proceed s to handle the alert condition. more than one device may have an active sm balert signal and attempt to communicate with the host. in this case, the device with the lowest address dominates the bus and succeeds in transmitting its address to the host. the d evice that succeeds disables its smbus a lert signal. if the host sees that the smbus a lert signal is still low, it continues to read addresses until all devices that need to talk to it have successfully transmitted their addres se s. example u se of smb u s alert response address the full sequence of steps that occurs when a n smbalert is generated and cleared is as follows: 1. a fault or warning is enabled using the alert1_config command , and the corresponding status bit f or the fault or warning goes from 0 to 1, indicating that the fault/ warning has just become active. 2. the gpox/ alertx pin becomes active (low) to signal that an smbalert is active. 3. the host processor issues a n smbus al ert r esponse a ddress to determine which device has an active alert. 4. if there are no other a ctive alerts from devices with lower i 2 c addresses, this device makes the gpox/ alertx pin inactive (high) during the nack bit period after it sen ds its address to the host processor. 5. if the gpox/ alertx pin stays low , the host processor must continue to issu e smbus a lert r esponse a ddress command s to devices to find out the addresses of all devices whose status it must check. 6. t he adm1275 continues to operate with the gpox/ alertx pin inactive and the contents of the status bytes unchanged until the host read s the status bytes and clear s them, or until a new fault occurs. that is, if a status bit for a fault/warning that is enabled on the gpox/ alertx pin and th at was not already active (equal to 1) goes from 0 to 1 , a new alert is generat ed , causing the gpox/ alertx pin to become active again.
adm1275 rev. b | page 36 of 48 pmbus command reference register addresses are in hexadecimal format. table 11. pmbus command summary command code command name smbus transaction type number of data bytes default value at reset 0x01 operation read/write byte 1 0x80 0x03 clear_faults send byte 0 not applicable 0x19 capability read byte 1 0xb0 0x42 vout_ov_warn_limit read/write word 2 0x0fff 0x43 vout_uv_warn_limit read/write word 2 0x0000 0x4a iout_oc_warn_limit read/write word 2 0x0fff 0x57 vin_ov_warn_limit read/write word 2 0x0fff 0x58 vin_uv_warn_limit read/write word 2 0x0000 0x78 status_byte read byte 1 0x00 0x79 status_word read word 2 0x0000 0x7a status_vout read byte 1 0x00 0x7b status_iout read byte 1 0x00 0x7c status_input read byte 1 0x00 0x80 status_mfr_specific read byte 1 0x00 0x88 read_vin read word 2 0x0000 0x8b read_vout read word 2 0x0000 0x8c read_iout read word 2 0x0000 0x98 pmbus_revision read byte 1 0x11 0x99 mfr_id block read 1 (byte count) + 3 (data) 0x03 + ascii adi 0x9a mfr_model block read 1 (byte count) + 9 (data) 0x09 + ascii adm1275-x 1 0x9b mfr_revision block read 1 (byt e count) + 1 (data) 0x01 + ascii 1 0xd0 peak_iout read/write word 2 0x0000 0xd1 peak_vin read/write word 2 0x0000 0xd2 peak_vout read/write word 2 0x0000 0xd3 pmon_control read/write byte 1 0x00 0xd4 pmon_config read/write byte 1 0x2c 0xd5 alert1_config read/write word 2 0x0000 0xd6 alert2_config read/write word 2 0x8000 0xd7 iout_warn2_limit read/write word 2 0x0000 0xd8 device_config read/write byte 1 0x00 0xd9 power_cycle send byte 0 not applicable 1 the character x in the string is 1, 2, or 3, depending on the model of the adm1275 that is being queried (a dm1275-1, adm1275 -2, or adm1275-3).
adm1275 rev. b | page 37 of 48 operation code: 0x01, r ead/ w rite b yte. value after reset: 0x80 . table 12 . bit descriptions for operation command bits bit name settings description 7 on 0 hot - swap output is disabled . 1 default. hot - swap output is enabled . [6:0] reserved 0 000000 always reads as 0 000000 . clear_faults code: 0x03, s end b yte, no data. capability code: 0x19, r ead byte . value after reset: 0xb0 . table 13 . bit descriptions for capability command bits bit name settings description 7 packet e rror c heckin g 1 always reads as 1 . p acket e rror c hecking (pec) is s upported . [6:5] maximum b us s peed 01 always reads as 01. maximum supported bus speed is 400 khz . 4 smbalert# 1 always reads as 1 . device supports smba lert and a lert r esponse a ddress (ara). [3:0] res erved 0 000 always reads as 0000. vout_ov_warn_limit code: 0x42, r ead/ w rite w ord. value after reset: 0x0fff . this command is supported on the adm1275 - 1 and the adm1275 - 3. the adm1 275- 2 does not have a vout pin. table 14 . bit descript ions for vout_ov_warn_limit command bits bit name settings description [15:12] reserved 0000 always reads as 0000 . [11:0] vout_ov_warn_limit over voltage thresho ld for the vout pin measurement, expressed in adc codes . vout_uv_warn_limit code: 0x43, r ea d/ w rite w ord. value after reset: 0x0000 . this command is supported on the adm1275 - 1 and the adm1275 - 3. the adm1 275- 2 does not have a vout pin. table 15 . bit descriptions for vout_uv_warn_limit command bits bit name settings descriptio n [15:12] reserved 0000 always reads as 0000 . [11:0] vout_uv_warn_limit under voltage threshold for the vout pin measurement , expressed in adc codes . iout_oc_warn_limit code: 0x4a, read/write word . value after reset: 0x0fff . table 16 . bit descriptions for iout_oc_warn_limit command bits bit name settings description [15:12] reserved 0000 always reads as 0000 . [11:0] iout_oc_warn_limit overcur rent threshold for the iout measurement through the sense resistor , expressed in adc cod es .
adm1275 rev. b | page 38 of 48 iout_warn2_limit code: 0xd7, read/write word . value after reset: 0x0000 . table 17 . bit descriptions for iout_warn2_limit command bits bit name settings description [15:12] reserved 0000 always reads as 0000 . [11:0] iout_warn2_ limit threshold for the iout measurement through the sense resistor , expressed in adc co des . this value can be either an under current or an overcur rent , depending on the state of the iout_warn2_select bit set using the device_config command. vin_ov_warn _limit code: 0x57, read/write word . value after reset: 0x0fff . table 18 . bit descriptions for vin_ov_warn_limit command bits bit name settings description [15:12] reserved 0000 always reads as 0000 . [11:0] vin_ov_warn_limit over vol tage threshold for the sense+ pin measurement , expressed in adc co des . vin_uv_warn_limit code: 0x58, read/write word . value after reset: 0x0000 . table 19 . bit descriptions for vin_uv_warn_limit command bits bit name settings descrip tion [15:12] reserved 0000 always reads as 0000 . [11:0] vin_uv_warn_limit under voltage threshold for the sense+ pin measurement , expressed in adc codes . status_byte code: 0x78, r ead b yte. value after reset: 0x00 . table 20 . bit de scriptions for status_byte command bits bit name behavior settings description 7 reserved 0 always reads as 0 . 6 hotswap_off live 0 the hot - swap gate drive output is enabled . 1 the hot - swap gate drive output is disabled, and the gate pin is pulled d own. this can be due to, for example, an overcur rent fault that causes the adm1275 to latch off, an undervoltage condition on the uv pin, or the use of the operation command to turn the output off. 5 reserved 0 always reads as 0. 4 iout_oc_fault latched 0 no overcur rent output fault detected . 1 the hot - swap controller detected an overcur rent condition and the time limit set by the capacitor on the timer pin has elapsed, causing the hot - swap gate drive to shut down. 3 vin_uv_fault latched 0 no under v oltage input fault detected on the uv pin . 1 an under voltage input fault was detected on the uv pin. 2 reserved 0 always reads as 0. 1 cml_error latched 0 no communications error detected on the i 2 c/pmbus interface . 1 an error was detected on th e i 2 c/pmbus i nterface. errors detected are unsupported command, i nvalid pec byte, and incorrectly structured message. 0 none_of_the_above live 0 no other active status bit to be reported by any other status command . 1 a ctive status bits are waiting to be read by one or more status commands . status_word code: 0x79, r ead word . value after reset: 0x0 000 .
adm1275 rev. b | page 39 of 48 table 21 . bit descriptions for status_ word command bits bit name behavior settings description 15 vout_status live 0 there are n o active status bits to be read by status_vout . 1 there are one or more active status bits to be read by status_vout . 14 iout_status live 0 there are no active status bits to be read by status_iout . 1 there are one or more active status bits to be read by status_iout . 13 vin_status live 0 there are no active status bits to be read by status_input . 1 there are one or more active status bits to be read by status_input . 12 mfr_status live 0 there are no active status bits to be read by status_mf r _specific . 1 there are one or more active status bits to be read by status_mfr_specific . 11 power_good# live 0 the voltage on the flb pin is above the required threshold, indicating that output power is considered good. this bit is the logical invers ion of the pwrgd pin on the part. 1 the voltage on the flb pin is below the required threshold, indicating that output power is considered bad. [10:8] reserved 000 always reads as 000. [7:0] status_byte this byte is the same as the byte returned b y the status_byte command . status_vout code: 0x7a, r ead b yte. value after reset: 0x00 . this command is supported on the adm1275 - 1 and the adm1275 - 3. the adm1275 - 2 does not have a vout pin. table 22 . bit descriptions for status_ vout command bits bit name behavior settings description 7 reserved 0 always reads as 0 . 6 vout_ov_warn latched 0 no overvo ltage condition on the output supply detected by the power monitor . 1 an overvo ltage condition on the output supply was detected by the power monitor . 5 vout_uv_warn latched 0 no under voltage condition on the output supply detected by the power monitor . 1 an under voltage condition on the output supply was detected by the power monitor . [4:0] reserved 00000 always reads as 00000. status_iout code: 0x7b, r ead b yte. value after reset: 0x00 . table 23 . bit descriptions for status_ iout command bits bit name behavior settings description 7 iout_oc_fault latched 0 no overcur rent output fault detected . 1 the hot - swap controller detected an overcur rent condition and the time limit set by the capacitor on the timer pin has elapsed, causing the hot - swap gate drive to shut down. 6 reserved 0 always reads as 0. 5 iout_oc_warn latched 0 no overcur rent condition o n the output supply detected by the power monitor using the iout_ oc_ warn_limit command . 1 an overcur rent condition was detected by the power monitor using the iout_ oc_ warn_limit command . [4:0] reserved 00000 always reads as 00000. status_input code : 0x7c, read byte . value after reset: 0x00 .
adm1275 rev. b | page 40 of 48 table 24 . bit descriptions for status_input command bits bit name behavior settings description 7 vin_ov_fault latched 0 no overvo ltage detected on the ov pin . 1 an overvo ltage was dete cted on the ov pin. 6 vin_ov_warn latched 0 no overvo ltage condition on the input supply detected by the power monitor . 1 an overvo ltage condition on the input supply was detected by the power monitor . 5 vin_uv_warn latched 0 no under voltag e condition on the input supply detected by the power monitor . 1 an under voltage condition on the input supply was detected by the power monitor . 4 vin_uv_fault latched 0 no under voltage detected on the uv pin . 1 an undervoltage was detected on th e uv pin. [3:0] reserved 0000 always reads as 0000. status_mfr_specific code: 0x80, read byte . value after reset: 0x00 . table 25 . bit descriptions for status_ mfr_specific command bits bit name behavior settings description 7 fet_ health_bad latched 0 fet behavior appears to be as expected . 1 fet behavior suggests th at th e fet may be shorted . 6 uv_cmp_out live 0 input voltage to uv pin is above threshold . 1 input voltage to uv pin is below threshold . 5 ov_cmp_out live 0 in put voltage to ov pin is below threshold . 1 input voltage to ov pin is above threshold . 4 reserved 0 always reads as 0. 3 hs_inlim latched 0 the adm1275 has not actively limited the current into the load . 1 the adm1275 h as actively limit ed curre nt into the load. this bit differ s from the iout_oc_fault bit in that the hs_inlim bit is set immediately, whereas the iout_oc_fault bit is not set unless the time limit set by the cap acitor on the t imer pin elapses. [2:1] hs_shutdown_cause latched 00 the adm1275 is either enabled and working correctly, or has been shut down using the operation command . 01 an iout_oc_fault condition occurred that caused the adm1275 to shut down . 10 a vin_uv_fault condition occurred that caused the adm1275 to shut d own . 11 a vin_ov_fault condition occurred that caused the adm1275 to shut down . 0 iout_warn2 latched 0 no overcurrent condition on the output supply detected by the power monitor using the iout_warn2_limit command . 1 a n under current or overcur rent condition on the output supply was detected by the power monitor using the iout_warn2_limit command . the polarity of the threshold condition is set by the iout_warn2_select bit using the device_config command. read_vin code: 0x88, read w ord. value after reset: 0x0000 . table 26 . bit descriptions for read_vin command bits bit name settings description [15:12] reserved 0000 always reads as 0000 . [11:0] vin input voltage from the sense+ pin measurement , expressed in adc codes .
adm1275 rev. b | page 41 of 48 read_vout code: 0x8b, read word. value after reset: 0x0000. this command is supported on the adm1275-1 and the adm1275-3. the adm1275-2 does not have a vout pin. table 27. bit descriptions for read_vout command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] vout output voltage from the vout pin measurement, expressed in adc codes. read_iout code: 0x8c, read word. value after reset: 0x0000. table 28. bit descriptions for read_iout command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] iout output current from the measurement through the sense resistor. pmbus_revision code: 0x98, read byte. value after reset: 0x11. table 29. bit descriptions for pmbus_revision command bits bit name settings description [7:4] part i revision 0001 always reads as 0001, pmbus specification part i, revision 1.1. [3:0] part ii revision 0001 always reads as 0001, pmbus specification part ii, revision 1.1. mfr_id code: 0x99, block read. value after reset: 0x03 + ascii adi. table 30. bit descriptions for mfr_id command byte byte name value description 0 byte count 0x03 always reads as 0x03, the number of data bytes that the block read command should expect to read. 1 character 1 0x41 or a always reads as 0x41. 2 character 2 0x44 or d always reads as 0x44. 3 character 3 0x49 or i always reads as 0x49. mfr_model code: 0x9a, block read. value after reset: 0x09 + ascii adm1275-x. table 31. bit descriptions for mfr_model command byte byte name value description 0 byte count 0x09 always reads as 0x09, the number of data bytes that the block read command should expect to read. 1 character 1 0x41 or a always reads as 0x41. 2 character 2 0x44 or d always reads as 0x44. 3 character 3 0x4d or m always reads as 0x4d. 4 character 4 0x31 or 1 always reads as 0x31. 5 character 5 0x32 or 2 always reads as 0x32. 6 character 6 0x37 or 7 always reads as 0x37. 7 character 7 0x35 or 5 always reads as 0x35. 8 character 8 0x2d or - always reads as 0x2d.
adm1275 rev. b | page 42 of 48 byte byte name value description 9 character 9 0x31 or 1 always reads as 0x31 on the adm1275-1. 0x32 or 2 always reads as 0x32 on the adm1275-2. 0x33 or 3 always reads as 0x33 on the adm1275-3. mfr_revision code: 0x9b, block read. value after reset: 0x01 + ascii 1. table 32. bit descriptions for mfr_revision command byte byte name value description 0 byte count 0x01 always reads as 0x01, the number of data bytes that the block read command should expect to read. 1 character 1 0x31 or 1 always reads as 0x31, revision 1 of the adm1275. peak_iout code: 0xd0, read/write word. value after reset: 0x0000 (writing 0x0000 clears the peak value). table 33. bit descriptions for peak_iout command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] peak_iout returns the peak iout current since the register was last cleared. peak_vin code: 0xd1, read/write word. value after reset: 0x0000 (writing 0x0000 clears the peak value). table 34. bit descriptions for peak_vin command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] peak_vin returns the peak vin voltage since the register was last cleared. peak_vout code: 0xd2, read/write word. value after reset: 0x0000 (writing 0x0000 clears the peak value). this command is supported on the adm1275-1 and the adm1275-3. the adm1275-2 does not have a vout pin. table 35. bit descriptions for peak_vout command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] peak_vout returns the peak vout voltage since the register was last cleared. pmon_control code: 0xd3, read/write byte. value after reset: 0x00. table 36. bit descriptions for pmon_control command bits bit name settings description [7:1] reserved 0000000 always reads as 0000000. 0 convert 0 default. power monitor is not running. 1 start the sampling of current and voltage with the power monitor. in single-shot mode, this bit clears itself after one complete cy cle. in continuous mode, this bit must be written to 0 to stop sampling.
adm1275 rev. b | page 43 of 48 pmon_config code: 0xd4, read/write byte. value after reset: 0x2c. modifying the power monitor settings while the power monitor is sampling is not supported. the power monitor must be stopped be fore any setting in table 37 is changed to ensure correct operation and to prevent any potential spurious data and status alerts bei ng generated. table 37. bit descriptions for pmon_config command bits bit name settings description 7 pmon_mode 0 default. this setting selects single-shot sampling mode. 1 this setting selects continuous sampling mode. 6 vin_vout_select 0 default. the power monitor will sample the input voltage on the sense+ pin. on the adm1275-2, this bit should always be written as 0. 1 the power monitor will sample th e output voltage on the vout pin. 5 vrange 0 sets the voltage input range fr om 0 v to 6 v (low input voltage range). 1 default. sets the voltage input range from 0 v to 20 v (high input voltage range). 4 reserved 0 reserved. this bit must always be written as 0. 3 reserved 1 default. this bit must be set to 1 for the power monitor current sense to operate correctly. [2:0] averaging 000 disables sample averaging for current and voltage. 001 sets sample averaging for current and voltage to 2 samples. 010 sets sample averaging for current and voltage to 4 samples. 011 sets sample averaging for current and voltage to 8 samples. 100 sets sample averaging for current and voltage to 16 samples. 101 sets sample averaging for current and voltage to 32 samples. 110 sets sample averaging for current and voltage to 64 samples. 111 sets sample averaging for current and voltage to 128 samples. alert1_config code: 0xd5, read/write word. value after reset: 0x0000. this command is supported on the adm1275-1 and the adm1275-2. the adm1275-3 does not have a gpo1/ alert1 /conv pin. table 38. bit descriptions for alert1_config command bits bit name settings description 15 fet_health_bad_en1 0 default. disa bles generation of smbalert when the fet_health_bad bit is set. 1 generate smbalert when the fet_health_bad bit is set. 14 iout_oc_fault_en1 0 default. disables generation of smbalert when the iout_oc_fault bit is set. 1 generate smbalert when the iout_oc_fault bit is set. 13 vin_ov_fault_en1 0 default. disables generation of smbalert when the vin_ov_fault bit is set. 1 generate smbalert when the vin_ov_fault bit is set. 12 vin_uv_fault_en1 0 default. disables generation of smbalert when the vin_uv_fault bit is set. 1 generate smbalert when the vin_uv_fault bit is set. 11 cml_error_en1 0 default. disabl es generation of smbalert when the cml_error bit is set. 1 generate smbalert when the cml_error bit is set. 10 iout_oc_warn_en1 0 default. disa bles generation of smbalert wh en the iout_oc_warn bit is set. 1 generate smbalert when the iout_oc_warn bit is set. 9 iout_warn2_en1 0 default. disa bles generation of smbalert when the iout_warn2 bit is set. 1 generate smbalert when the iout_warn2 bit is set. 8 vin_ov_warn_en1 0 default. disa bles generation of smbalert wh en the vin_ov_warn bit is set. 1 generate smbalert when the vin_ov_warn bit is set. 7 vin_uv_warn_en1 0 default. disables generation of smbalert when the vin_uv_warn bit is set. 1 generate smbalert when the vin_uv_warn bit is set. 6 vout_ov_warn_en1 0 default. disa bles generation of smbalert wh en the vout_ov_warn bit is set. 1 generate smbalert when the vout_ov_warn bit is set.
adm1275 rev. b | page 44 of 48 bits bit name settings description 5 vout_uv_warn_en1 0 default. disables generation of smbalert when the vout_uv_warn bit is set. 1 generate smbalert when the vout_uv_warn bit is set. 4 hs_inlim_en1 0 default. disables generation of smbalert when the hs_inlim bit is set. 1 generate smbalert when the hs_inlim bit is set. 3 invert_smbalert_1 0 default. smbalert is active low when a fault/warning bit that is enabled becomes set. 1 smbalert is active high when a faul t/warning bit that is enabled becomes set. 2 convert_en 0 default. gpo1/alert1 /conv is configured as an output pin. 1 gpo1/alert1 /conv is configured as an input pin. all other settings in alert1_config are ignored. 1 gpo1_en 0 default. gpo1/alert1 /conv can be configured as either a power monitor convert input or an smbalert output. 1 gpo1/alert1 /conv is configured as a general- purpose output unless convert_en is set to 1. 0 gpo1_data 0 default. sets gpo1/alert1 /conv low when configured as a general-purpose output. 1 sets gpo1/alert1 /conv high when configured as a general-purpose output. alert2_config code: 0xd6, read/write word. value after reset: 0x8000. this command is supported on the adm1275-1 and the adm1275-3. the adm1275-2 does not have a gpo2/ alert2 pin. table 39. bit descriptions for alert2_config command bits bit name settings description 15 fet_health_bad_en2 0 disables generation of smbalert when the fet_health_bad bit is set. 1 default. generate smbalert when the fet_heal th_bad bit is set. this bit is active from power-up so that a fet problem can be detected and flagged immediately without the need for software to set this bit. 14 iout_oc_fault_en2 0 default. disables generation of smbalert when the iout_oc_fault bit is set. 1 generate smbalert when the iout_oc_fault bit is set. 13 vin_ov_fault_en2 0 default. disables generation of smbalert when the vin_ov_fault bit is set. 1 generate smbalert when the vin_ov_fault bit is set. 12 vin_uv_fault_en2 0 default. disables generation of smbalert when the vin_uv_fault bit is set. 1 generate smbalert when the vin_uv_fault bit is set. 11 cml_error_en2 0 default. disabl es generation of smbalert when the cml_error bit is set. 1 generate smbalert when the cml_error bit is set. 10 iout_oc_warn_en2 0 default. disa bles generation of smbalert wh en the iout_oc_warn bit is set. 1 generate smbalert when the iout_oc_warn bit is set. 9 iout_warn2_en2 0 default. disa bles generation of smbalert when the iout_warn2 bit is set. 1 generate smbalert when the iout_warn2 bit is set. 8 vin_ov_warn_en2 0 default. disa bles generation of smbalert wh en the vin_ov_warn bit is set. 1 generate smbalert when the vin_ov_warn bit is set. 7 vin_uv_warn_en2 0 default. disables generation of smbalert when the vin_uv_warn bit is set. 1 generate smbalert when the vin_uv_warn bit is set. 6 vout_ov_warn_en2 0 default. disa bles generation of smbalert wh en the vout_ov_warn bit is set. 1 generate smbalert when the vout_ov_warn bit is set. 5 vout_uv_warn_en2 0 default. disables generation of smbalert when the vout_uv_warn bit is set. 1 generate smbalert when the vout_uv_warn bit is set. 4 hs_inlim_en2 0 default. disables generation of smbalert when the hs_inlim bit is set. 1 generate smbalert when the hs_inlim bit is set. 3 invert_smbalert_2 0 default. smbalert is active low when a fault/warning bit that is enabled becomes set. 1 smbalert is active high when a faul t/warning bit that is enabled becomes set. 2 reserved 0 always reads as 0.
adm1275 rev. b | page 45 of 48 bits bit name settings description 1 gpo2_en 0 default. gpo/alert2 is configured as an smbalert output. 1 gpo/alert2 is configured as a general-purpose output. 0 gpo2_data 0 default. sets gpo/alert2 low when configured as a general-purpose output. 1 sets gpo/alert2 high when configured as a general-purpose output. device_config code: 0xd8, read/write byte. value after reset: 0x00. table 40. bit descriptions for device_config command bits bit name settings description 7 oc_glitch_time 0 default. the long duration glitch filter is used when a severe overcurrent fault is detected. 1 the short duration glitch filter is used when a severe overcurrent fault is detected. 6 flb_disable 0 default. foldback is enabled and can affect the hot-swap current sense limit. 1 foldback is disabled and does not affect the hot-swap current sense limit. this setting can be useful if the sole purpose of the flb pin is to act as a power-good input. 5 operation_cmd_en 0 default. the operation command is disabl ed, and the adm1275 issues a nack if the command is received. this setting pr ovides some protection against a card accidentally turning itself off. 1 the operation command is enable d, and the adm1275 responds to it. 4 iout_warn2_select 0 default. configures iout_w arn2_limit as an unde rcurrent threshold. 1 configures iout_warn2_limit as an overcurrent threshold. [3:0] reserved 0000 always reads as 0000. power_cycle code: 0xd9, send byte, no data.
adm1275 rev. b | page 46 of 48 outline dimensions compliant t o jedec st andards mo-13 7-ab controll ing dimensions are in inches; millim eter dimensions (in p arentheses ) are rounded-off inch equiv alents for reference onl y and are not appro pria te for use in design. 16 9 8 1 s e a t i n g p l a n e 0 . 0 1 0 ( 0 . 2 5 ) 0 . 0 0 4 ( 0 . 1 0 ) 0 . 0 1 2 ( 0 . 3 0 ) 0 . 0 0 8 ( 0 . 2 0 ) 0 . 0 2 5 ( 0 . 6 4 ) b s c 0 . 0 4 1 ( 1 . 0 4 ) r e f 0 . 0 1 0 ( 0 . 2 5 ) 0 . 0 0 6 ( 0 . 1 5 ) 0 . 0 5 0 ( 1 . 2 7 ) 0 . 0 1 6 ( 0 . 4 1 ) 0 . 0 2 0 ( 0 . 5 1 ) 0 . 0 1 0 ( 0 . 2 5 ) 8 0 coplanarity 0.004 (0.10) 0 . 0 6 5 ( 1 . 6 5 ) 0 . 0 4 9 ( 1 . 2 5 ) 0 . 0 6 9 ( 1 . 7 5 ) 0 . 0 5 3 ( 1 . 3 5 ) 0 . 1 9 7 ( 5 . 0 0 ) 0 . 1 9 3 ( 4 . 9 0 ) 0 . 1 8 9 ( 4 . 8 0 ) 0 . 1 5 8 ( 4 . 0 1 ) 0 . 1 5 4 ( 3 . 9 1 ) 0 . 1 5 0 ( 3 . 8 1 ) 0 . 2 4 4 ( 6 . 2 0 ) 0 . 2 3 6 ( 5 . 9 9 ) 0 . 2 2 8 ( 5 . 7 9 ) 01-28-2 008-a figure 66 . 16 - lead shrink small outline package [qsop] (rq - 16) dimensions shown in inches and (millimeters) compliant t o jedec st andards mo-137-ad controlling dimensions are in inches; millimeter dimensions (in p arentheses) are rounded-off inch equiv alents for reference onl y and are not appropria te for use in design. 20 1 1 10 1 s e a t i n g p l a n e 0 . 0 1 0 ( 0 . 2 5 ) 0 . 0 0 4 ( 0 . 1 0 ) 0 . 0 1 2 ( 0 . 3 0 ) 0 . 0 0 8 ( 0 . 2 0 ) 0 . 0 2 5 ( 0 . 6 4 ) b s c 0 . 0 4 1 ( 1 . 0 4 ) r e f 0 . 0 1 0 ( 0 . 2 5 ) 0 . 0 0 6 ( 0 . 1 5 ) 0 . 0 5 0 ( 1 . 2 7 ) 0 . 0 1 6 ( 0 . 4 1 ) 0 . 0 2 0 ( 0 . 5 1 ) 0 . 0 1 0 ( 0 . 2 5 ) 8 0 coplanarity 0.004 (0.10) 0 . 0 6 5 ( 1 . 6 5 ) 0 . 0 4 9 ( 1 . 2 5 ) 0 . 0 6 9 ( 1 . 7 5 ) 0 . 0 5 3 ( 1 . 3 5 ) 0 . 3 4 5 ( 8 . 7 6 ) 0 . 3 4 1 ( 8 . 6 6 ) 0 . 3 3 7 ( 8 . 5 5 ) 0 . 1 5 8 ( 4 . 0 1 ) 0 . 1 5 4 ( 3 . 9 1 ) 0 . 1 5 0 ( 3 . 8 1 ) 0 . 2 4 4 ( 6 . 2 0 ) 0 . 2 3 6 ( 5 . 9 9 ) 0 . 2 2 8 ( 5 . 7 9 ) 08-1 9-2008-a figure 67 . 20 - lea d shrink small outline package [qsop] (rq - 20) dimensions shown in inches and (millimeters)
adm1275 rev. b | page 47 of 48 compliant to jedec standards mo-220-whhc. 111908-a 0.65 bsc 0.70 0.60 0.40 0.35 0.28 0.23 bot t om view top view exposed pa d pin 1 indic a t or 5.10 5.00 sq 4.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 3.25 3.10 sq 2.95 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 68 . 20 - lead lead frame chip scale package [lfcsp _wq ] 5 mm 5 mm body, very very thin quad (cp - 20 - 9) dimensions shown in millimete rs ordering guide model 1 temperature range package description package option adm1275 - 1arqz ? 40 c to +85 c 20-l ead qsop rq -20 adm1275 - 1arqz -r7 ? 40 c to +85 c 20-l ead qsop rq -20 adm1275 - 1acp z ? 40 c to +85 c 20- lead lfcsp _wq cp -20-9 adm1275 - 1acp z -r7 ? 40 c to +85 c 20- lead lfcsp _wq cp -20-9 adm1275 - 2arqz ? 40 c to +85 c 16-l ead qsop rq -16 adm1275 - 2arqz -r7 ? 40 c to +85 c 16-l ead qsop rq -16 adm1275 - 3arqz ? 40 c to +85 c 20-l ead qsop rq -20 adm1275 - 3arqz -r7 ? 40 c to +85 c 20-l ead qsop rq -20 adm1275 - 3acp z ? 4 0 c to +85 c 20- lead lfcsp _wq cp -20-9 adm1275 - 3acp z -r7 ? 40 c to +85 c 20- lead lfcsp _wq cp -20-9 eval - adm1275ebz evaluation board 1 z = rohs compliant part.
adm1275 rev. b | page 48 of 48 notes i 2 c refers to a communications protocol originally developed by philips semicon ductors (now nxp semiconductors). ? 2010 C 2011 analog devices, inc . all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08931 - 0- 6/11(b)

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